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[1/2] dt-bindings: pinctrl: qcom: Add SDX55 pinctrl bindings

Message ID 20201028083017.611810-1-vkoul@kernel.org
State Changes Requested
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Series [1/2] dt-bindings: pinctrl: qcom: Add SDX55 pinctrl bindings | expand

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Commit Message

Vinod Koul Oct. 28, 2020, 8:30 a.m. UTC
Add device tree binding Documentation details for Qualcomm SDX55
pinctrl driver.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 .../bindings/pinctrl/qcom,sdx55-pinctrl.yaml  | 144 ++++++++++++++++++
 1 file changed, 144 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml

Comments

Vinod Koul Oct. 29, 2020, 11:13 a.m. UTC | #1
On 28-10-20, 11:35, Bjorn Andersson wrote:
> On Wed 28 Oct 03:30 CDT 2020, Vinod Koul wrote:
> > diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c
> [..]
> > +static const struct msm_function sdx55_functions[] = {
> [..]
> > +	FUNCTION(qdss_gpio),
> > +	FUNCTION(qdss_gpio0),
> > +	FUNCTION(qdss_gpio1),
> > +	FUNCTION(qdss_gpio2),
> > +	FUNCTION(qdss_gpio3),
> > +	FUNCTION(qdss_gpio4),
> > +	FUNCTION(qdss_gpio5),
> > +	FUNCTION(qdss_gpio6),
> > +	FUNCTION(qdss_gpio7),
> > +	FUNCTION(qdss_gpio8),
> > +	FUNCTION(qdss_gpio9),
> > +	FUNCTION(qdss_gpio10),
> > +	FUNCTION(qdss_gpio11),
> > +	FUNCTION(qdss_gpio12),
> > +	FUNCTION(qdss_gpio13),
> > +	FUNCTION(qdss_gpio14),
> > +	FUNCTION(qdss_gpio15),
> 
> As there are no overlaps within pingroups you can keep qdss_gpio as a
> single function.

Okay so is the generic guidance to group things into single function
when they do not overlap?

> 
> > +	FUNCTION(qdss_stm0),
> > +	FUNCTION(qdss_stm1),
> > +	FUNCTION(qdss_stm2),
> > +	FUNCTION(qdss_stm3),
> > +	FUNCTION(qdss_stm4),
> > +	FUNCTION(qdss_stm5),
> > +	FUNCTION(qdss_stm6),
> > +	FUNCTION(qdss_stm7),
> > +	FUNCTION(qdss_stm8),
> > +	FUNCTION(qdss_stm9),
> > +	FUNCTION(qdss_stm10),
> > +	FUNCTION(qdss_stm11),
> > +	FUNCTION(qdss_stm12),
> > +	FUNCTION(qdss_stm13),
> > +	FUNCTION(qdss_stm14),
> > +	FUNCTION(qdss_stm15),
> > +	FUNCTION(qdss_stm16),
> > +	FUNCTION(qdss_stm17),
> > +	FUNCTION(qdss_stm18),
> > +	FUNCTION(qdss_stm19),
> > +	FUNCTION(qdss_stm20),
> > +	FUNCTION(qdss_stm21),
> > +	FUNCTION(qdss_stm22),
> > +	FUNCTION(qdss_stm23),
> > +	FUNCTION(qdss_stm24),
> > +	FUNCTION(qdss_stm25),
> > +	FUNCTION(qdss_stm26),
> > +	FUNCTION(qdss_stm27),
> > +	FUNCTION(qdss_stm28),
> > +	FUNCTION(qdss_stm29),
> > +	FUNCTION(qdss_stm30),
> > +	FUNCTION(qdss_stm31),
> 
> Ditto.
> 
> > +	FUNCTION(qlink0_en),
> > +	FUNCTION(qlink0_req),
> > +	FUNCTION(qlink0_wmss),
> > +	FUNCTION(qlink1_en),
> > +	FUNCTION(qlink1_req),
> > +	FUNCTION(qlink1_wmss),
> > +	FUNCTION(spmi_coex),
> > +	FUNCTION(sec_mi2s),
> > +	FUNCTION(spmi_vgi),
> > +	FUNCTION(tgu_ch0),
> > +	FUNCTION(uim1_clk),
> > +	FUNCTION(uim1_data),
> > +	FUNCTION(uim1_present),
> > +	FUNCTION(uim1_reset),
> > +	FUNCTION(uim2_clk),
> > +	FUNCTION(uim2_data),
> > +	FUNCTION(uim2_present),
> > +	FUNCTION(uim2_reset),
> > +	FUNCTION(usb2phy_ac),
> > +	FUNCTION(vsense_trigger),
> > +};
> > +
> > +/* Every pin is maintained as a single group, and missing or non-existing pin
> > + * would be maintained as dummy group to synchronize pin group index with
> > + * pin descriptor registered with pinctrl core.
> > + * Clients would not be able to request these dummy pin groups.
> > + */
> > +static const struct msm_pingroup sdx55_groups[] = {
> > +	[0] = PINGROUP(0, uim2_data, blsp_uart1, qdss_stm31, ebi0_wrcdc, _,
> > +		       _, _, _, _),
> 
> Please break the 80 character suggestion and leave these unwrapped.

120 now ;-)

> 
> [..]
> > +	[108] = UFS_RESET(ufs_reset, 0x0),
> 
> SDX55 doesn't have UFS support and I'm not able to find any UFS_RESET
> register in the TLMM block. So I suspect this is a copy paste issue
> somewhere.
> 
> PS. Don't forget to drop the macro, if we don't need it.

I will check though I have not seen UFS block. But yes this did exist in
downstream!

> 
> > +	[109] = SDC_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
> > +	[110] = SDC_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
> > +	[111] = SDC_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
> > +	[112] = SDC_PINGROUP(sdc1_data, 0x9a000, 9, 0),
> > +};
> > +
> > +static const struct msm_pinctrl_soc_data sdx55_pinctrl = {
> > +	.pins = sdx55_pins,
> > +	.npins = ARRAY_SIZE(sdx55_pins),
> > +	.functions = sdx55_functions,
> > +	.nfunctions = ARRAY_SIZE(sdx55_functions),
> > +	.groups = sdx55_groups,
> > +	.ngroups = ARRAY_SIZE(sdx55_groups),
> > +	.ngpios = 108,
> 
> If we had UFS_RESET, this should include it; i.e. be 109.

Okay will check and update

Thanks for quick review
Rob Herring Oct. 30, 2020, 7:24 p.m. UTC | #2
On Wed, Oct 28, 2020 at 02:00:16PM +0530, Vinod Koul wrote:
> Add device tree binding Documentation details for Qualcomm SDX55
> pinctrl driver.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../bindings/pinctrl/qcom,sdx55-pinctrl.yaml  | 144 ++++++++++++++++++
>  1 file changed, 144 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
> new file mode 100644
> index 000000000000..2dd045a2fb03
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. SDX55 TLMM block
> +
> +maintainers:
> +  - Vinod Koul <vkoul@kernel.org>
> +
> +description: |
> +  This binding describes the Top Level Mode Multiplexer block found in the
> +  SDX55 platform.
> +
> +properties:
> +  compatible:
> +    const: qcom,sdx55-pinctrl
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    description: Specifies the TLMM summary IRQ
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    description:
> +      Specifies the PIN numbers and Flags, as defined in defined in
> +      include/dt-bindings/interrupt-controller/irq.h
> +    const: 2
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    description: Specifying the pin number and flags, as defined in
> +      include/dt-bindings/gpio/gpio.h
> +    const: 2
> +
> +  gpio-ranges:
> +    maxItems: 1
> +
> +  wakeup-parent:
> +    maxItems: 1
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> +  '^.*$':
> +    if:
> +      type: object
> +    then:

For new bindings, just name the nodes '-pins$' and forget this hack.

> +      properties:
> +        pins:
> +          description:
> +            List of gpio pins affected by the properties specified in this
> +            subnode.
> +          items:
> +            oneOf:
> +              - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
> +              - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
> +          minItems: 1
> +          maxItems: 36
> +
> +        function:
> +          description:
> +            Specify the alternative function to be configured for the specified
> +            pins.
> +
> +          enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
> +                  blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
> +                  blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
> +                  blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
> +                  cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
> +                  ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
> +                  emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
> +                  gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
> +                  mgpi_clk, m_voc, native_char, native_char0, native_char1,
> +                  native_char2, native_char3, native_tsens, native_tsense,
> +                  nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
> +                  pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
> +                  qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
> +                  qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
> +                  qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
> +                  qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
> +                  qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
> +                  qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
> +                  qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
> +                  qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
> +                  qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
> +                  qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
> +                  qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
> +                  spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
> +                  uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
> +                  uim2_reset, usb2phy_ac, vsense_trigger ]
> +
> +        drive-strength:
> +          enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +          default: 2
> +          description:
> +            Selects the drive strength for the specified pins, in mA.
> +
> +        bias-pull-down: true
> +
> +        bias-pull-up: true
> +
> +        bias-disable: true
> +
> +        output-high: true
> +
> +        output-low: true
> +
> +      required:
> +        - pins
> +        - function
> +
> +      additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - gpio-controller
> +  - '#gpio-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +        #include <dt-bindings/interrupt-controller/arm-gic.h>
> +        pinctrl@1f00000 {
> +                compatible = "qcom,sdx55-pinctrl";
> +                reg = <0x0f100000 0x300000>;
> +                interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
> +                #interrupt-cells = <2>;
> +                interrupt-controller;
> +                gpio-controller;
> +                #gpio-cells = <2>;
> +        };
> +
> +...
> -- 
> 2.26.2
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
new file mode 100644
index 000000000000..2dd045a2fb03
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml
@@ -0,0 +1,144 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SDX55 TLMM block
+
+maintainers:
+  - Vinod Koul <vkoul@kernel.org>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  SDX55 platform.
+
+properties:
+  compatible:
+    const: qcom,sdx55-pinctrl
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: Specifies the TLMM summary IRQ
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    description:
+      Specifies the PIN numbers and Flags, as defined in defined in
+      include/dt-bindings/interrupt-controller/irq.h
+    const: 2
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    description: Specifying the pin number and flags, as defined in
+      include/dt-bindings/gpio/gpio.h
+    const: 2
+
+  gpio-ranges:
+    maxItems: 1
+
+  wakeup-parent:
+    maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+  '^.*$':
+    if:
+      type: object
+    then:
+      properties:
+        pins:
+          description:
+            List of gpio pins affected by the properties specified in this
+            subnode.
+          items:
+            oneOf:
+              - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
+              - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
+          minItems: 1
+          maxItems: 36
+
+        function:
+          description:
+            Specify the alternative function to be configured for the specified
+            pins.
+
+          enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
+                  blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
+                  blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
+                  blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
+                  cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+                  ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
+                  emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
+                  gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
+                  mgpi_clk, m_voc, native_char, native_char0, native_char1,
+                  native_char2, native_char3, native_tsens, native_tsense,
+                  nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
+                  pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
+                  qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
+                  qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
+                  qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+                  qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
+                  qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
+                  qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
+                  qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
+                  qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
+                  qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
+                  qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
+                  qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
+                  spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
+                  uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
+                  uim2_reset, usb2phy_ac, vsense_trigger ]
+
+        drive-strength:
+          enum: [2, 4, 6, 8, 10, 12, 14, 16]
+          default: 2
+          description:
+            Selects the drive strength for the specified pins, in mA.
+
+        bias-pull-down: true
+
+        bias-pull-up: true
+
+        bias-disable: true
+
+        output-high: true
+
+        output-low: true
+
+      required:
+        - pins
+        - function
+
+      additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-controller
+  - '#interrupt-cells'
+  - gpio-controller
+  - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+        #include <dt-bindings/interrupt-controller/arm-gic.h>
+        pinctrl@1f00000 {
+                compatible = "qcom,sdx55-pinctrl";
+                reg = <0x0f100000 0x300000>;
+                interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+...