diff mbox series

[v6,1/3] dt-binding: reset-controller: mediatek: add YAML schemas

Message ID 20200930022159.5559-2-crystal.guo@mediatek.com
State Needs Review / ACK
Headers show
Series introduce TI reset controller for MT8192 SoC | expand

Checks

Context Check Description
robh/dt-meta-schema success
robh/checkpatch success

Commit Message

Crystal Guo Sept. 30, 2020, 2:21 a.m. UTC
Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset
management, and is suitable for Mediatek SoCs.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

Comments

Crystal Guo Oct. 14, 2020, 1:30 p.m. UTC | #1
Hi Maintainers,

Gentle ping for this patch set.

Many thanks
Crystal

On Wed, 2020-09-30 at 10:21 +0800, Crystal Guo wrote:
> Add a YAML documentation for Mediatek, which uses ti reset-controller
> driver directly. The TI reset controller provides a common reset
> management, and is suitable for Mediatek SoCs.
> 
> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> ---
>  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> new file mode 100644
> index 000000000000..7871550c3c69
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Reset Controller
> +
> +maintainers:
> +  - Crystal Guo <crystal.guo@mediatek.com>
> +
> +description:
> +  The bindings describe the reset-controller for Mediatek SoCs,
> +  which is based on TI reset controller. For more detail, please
> +  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +properties:
> +  compatible:
> +    const: mediatek,syscon-reset
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  mediatek,reset-bits:
> +    description: >
> +      Contains the reset control register information, please refer to
> +      Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +required:
> +  - compatible
> +  - '#reset-cells'
> +  - mediatek,reset-bits
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/ti-syscon.h>
> +    infracfg: infracfg@10001000 {
> +        compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> +        reg = <0 0x10001000>;
> +        #clock-cells = <1>;
> +
> +        infracfg_rst: reset-controller {
> +            compatible = "mediatek,syscon-reset";
> +            #reset-cells = <1>;
> +            mediatek,reset-bits = <
> +               0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
> +            >;
> +        };
> +    };
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index 000000000000..7871550c3c69
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+  - Crystal Guo <crystal.guo@mediatek.com>
+
+description:
+  The bindings describe the reset-controller for Mediatek SoCs,
+  which is based on TI reset controller. For more detail, please
+  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+  compatible:
+    const: mediatek,syscon-reset
+
+  '#reset-cells':
+    const: 1
+
+  mediatek,reset-bits:
+    description: >
+      Contains the reset control register information, please refer to
+      Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+  - compatible
+  - '#reset-cells'
+  - mediatek,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/ti-syscon.h>
+    infracfg: infracfg@10001000 {
+        compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+        reg = <0 0x10001000>;
+        #clock-cells = <1>;
+
+        infracfg_rst: reset-controller {
+            compatible = "mediatek,syscon-reset";
+            #reset-cells = <1>;
+            mediatek,reset-bits = <
+               0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+            >;
+        };
+    };