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[1/2] dt-bindings: interrupt-controller: add Hisilicon SD5203 vector interrupt controller

Message ID 20200903120504.2308-2-thunder.leizhen@huawei.com
State Changes Requested, archived
Headers show
Series add support for Hisilicon SD5203 vector interrupt controller | expand

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robh/checkpatch warning total: 0 errors, 1 warnings, 27 lines checked

Commit Message

Leizhen (ThunderTown) Sept. 3, 2020, 12:05 p.m. UTC 
Add DT bindings for the Hisilicon SD5203 vector interrupt controller.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt

Comments

Rob Herring (Arm) Sept. 14, 2020, 8:31 p.m. UTC | #1 
On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
> 
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> ---
>  .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++

Bindings should be in DT schema format now.

>  1 file changed, 27 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> new file mode 100644
> index 000000000000..a08292e868b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
> @@ -0,0 +1,27 @@
> +Hisilicon SD5203 vector interrupt controller (VIC)
> +
> +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but
> +there's something special:
> +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
> +   FINALSTATUS are 32 bits.
> +2. There is only one VIC, it's used as primary interrupt controller.
> +
> +Required properties:
> +- compatible: shall be "hisilicon,sd5203-vic"
> +- reg: physical base address of the controller and length of memory mapped
> +  region starting with ENABLE_LOW register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +
> +Example:
> +	vic: interrupt-controller@10130000 {
> +		compatible = "hisilicon,sd5203-vic";
> +		reg = <0x10130000 0x1000>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +	};
> -- 
> 2.26.0.106.g9fadedd
> 
>
Leizhen (ThunderTown) Sept. 15, 2020, 6:12 a.m. UTC | #2 
On 2020/9/15 4:31, Rob Herring wrote:
> On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
>> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>> ---
>>  .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++
> 
> Bindings should be in DT schema format now.

Hi, Rob Herring:

As Marc Zyngier's suggestion, I discarded adding an independent SD5203-VIC
driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain.
So this new file was also dropped. Now, I updated the descriptions in the existing
file "snps,dw-apb-ictl.txt" in the following versions.

> 
>>  1 file changed, 27 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>> new file mode 100644
>> index 000000000000..a08292e868b0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>> @@ -0,0 +1,27 @@
>> +Hisilicon SD5203 vector interrupt controller (VIC)
>> +
>> +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but
>> +there's something special:
>> +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
>> +   FINALSTATUS are 32 bits.
>> +2. There is only one VIC, it's used as primary interrupt controller.
>> +
>> +Required properties:
>> +- compatible: shall be "hisilicon,sd5203-vic"
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region starting with ENABLE_LOW register
>> +- interrupt-controller: identifies the node as an interrupt controller
>> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
>> +
>> +The interrupt sources map to the corresponding bits in the interrupt
>> +registers, i.e.
>> +- 0 maps to bit 0 of low interrupts,
>> +- 1 maps to bit 1 of low interrupts,
>> +
>> +Example:
>> +	vic: interrupt-controller@10130000 {
>> +		compatible = "hisilicon,sd5203-vic";
>> +		reg = <0x10130000 0x1000>;
>> +		interrupt-controller;
>> +		#interrupt-cells = <1>;
>> +	};
>> -- 
>> 2.26.0.106.g9fadedd
>>
>>
> 
> .
>
Leizhen (ThunderTown) Sept. 17, 2020, 3:30 a.m. UTC | #3 
On 2020/9/15 14:12, Leizhen (ThunderTown) wrote:
> 
> 
> On 2020/9/15 4:31, Rob Herring wrote:
>> On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
>>> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
>>>
>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>>> ---
>>>  .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++
>>
>> Bindings should be in DT schema format now.

Do I need to change the existing "snps,dw-apb-ictl.txt" to DT schema format?

> 
> Hi, Rob Herring:
> 
> As Marc Zyngier's suggestion, I discarded adding an independent SD5203-VIC
> driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain.
> So this new file was also dropped. Now, I updated the descriptions in the existing
> file "snps,dw-apb-ictl.txt" in the following versions.
> 
>>
>>>  1 file changed, 27 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>>> new file mode 100644
>>> index 000000000000..a08292e868b0
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
>>> @@ -0,0 +1,27 @@
>>> +Hisilicon SD5203 vector interrupt controller (VIC)
>>> +
>>> +Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but
>>> +there's something special:
>>> +1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
>>> +   FINALSTATUS are 32 bits.
>>> +2. There is only one VIC, it's used as primary interrupt controller.
>>> +
>>> +Required properties:
>>> +- compatible: shall be "hisilicon,sd5203-vic"
>>> +- reg: physical base address of the controller and length of memory mapped
>>> +  region starting with ENABLE_LOW register
>>> +- interrupt-controller: identifies the node as an interrupt controller
>>> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
>>> +
>>> +The interrupt sources map to the corresponding bits in the interrupt
>>> +registers, i.e.
>>> +- 0 maps to bit 0 of low interrupts,
>>> +- 1 maps to bit 1 of low interrupts,
>>> +
>>> +Example:
>>> +	vic: interrupt-controller@10130000 {
>>> +		compatible = "hisilicon,sd5203-vic";
>>> +		reg = <0x10130000 0x1000>;
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <1>;
>>> +	};
>>> -- 
>>> 2.26.0.106.g9fadedd
>>>
>>>
>>
>> .
>>
Rob Herring (Arm) Sept. 18, 2020, 6:55 p.m. UTC | #4 
On Wed, Sep 16, 2020 at 9:30 PM Leizhen (ThunderTown)
<thunder.leizhen@huawei.com> wrote:
>
>
>
> On 2020/9/15 14:12, Leizhen (ThunderTown) wrote:
> >
> >
> > On 2020/9/15 4:31, Rob Herring wrote:
> >> On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
> >>> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
> >>>
> >>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> >>> ---
> >>>  .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++
> >>
> >> Bindings should be in DT schema format now.
>
> Do I need to change the existing "snps,dw-apb-ictl.txt" to DT schema format?

That would be nice, but not necessary for minor changes.

Rob
Leizhen (ThunderTown) Sept. 19, 2020, 2:02 a.m. UTC | #5 
On 2020/9/19 2:55, Rob Herring wrote:
> On Wed, Sep 16, 2020 at 9:30 PM Leizhen (ThunderTown)
> <thunder.leizhen@huawei.com> wrote:
>>
>>
>>
>> On 2020/9/15 14:12, Leizhen (ThunderTown) wrote:
>>>
>>>
>>> On 2020/9/15 4:31, Rob Herring wrote:
>>>> On Thu, Sep 03, 2020 at 08:05:03PM +0800, Zhen Lei wrote:
>>>>> Add DT bindings for the Hisilicon SD5203 vector interrupt controller.
>>>>>
>>>>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
>>>>> ---
>>>>>  .../hisilicon,sd5203-vic.txt                  | 27 +++++++++++++++++++
>>>>
>>>> Bindings should be in DT schema format now.
>>
>> Do I need to change the existing "snps,dw-apb-ictl.txt" to DT schema format?
> 
> That would be nice, but not necessary for minor changes.

I had done it before you replied to me. Can you check it out?

https://www.spinics.net/lists/devicetree/msg378632.html

> 
> Rob
> 
> .
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
new file mode 100644
index 000000000000..a08292e868b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,sd5203-vic.txt
@@ -0,0 +1,27 @@ 
+Hisilicon SD5203 vector interrupt controller (VIC)
+
+Hisilicon SD5203 VIC based on Synopsys DesignWare APB interrupt controller, but
+there's something special:
+1. The maximum number of irqs supported is 32. The registers ENABLE, MASK and
+   FINALSTATUS are 32 bits.
+2. There is only one VIC, it's used as primary interrupt controller.
+
+Required properties:
+- compatible: shall be "hisilicon,sd5203-vic"
+- reg: physical base address of the controller and length of memory mapped
+  region starting with ENABLE_LOW register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
+
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of low interrupts,
+- 1 maps to bit 1 of low interrupts,
+
+Example:
+	vic: interrupt-controller@10130000 {
+		compatible = "hisilicon,sd5203-vic";
+		reg = <0x10130000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};