From patchwork Fri Aug 14 06:04:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 1344639 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=IThPlJJ9; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BSXx01YbHz9sTR for ; Fri, 14 Aug 2020 16:05:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726110AbgHNGFe (ORCPT ); Fri, 14 Aug 2020 02:05:34 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:29563 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726139AbgHNGFd (ORCPT ); Fri, 14 Aug 2020 02:05:33 -0400 X-UUID: 2d99217e74c84f8ba20a5b274f5aa6fd-20200814 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qLDakBeiLbmANdjXt3bA+JvN+jwjGyd1xiqJb9UZTck=; b=IThPlJJ9LO0zjrFTZu+Sn3J9t+ddJxMcvj13LvIw+ZfS/ys8AIg2xg5m7WxsOrU52eDM7njvUXkXI35ORlDpsqWH0Jrm0hVYBiXiXvFauqwizWHdfpKHmXLG5Y1G4Lz/ji3Pn1W+phuGyIwMFLWGPVqXHUKiQ0Jf9SycrFpRrgM=; X-UUID: 2d99217e74c84f8ba20a5b274f5aa6fd-20200814 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 734366943; Fri, 14 Aug 2020 14:05:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 14 Aug 2020 14:05:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 14 Aug 2020 14:05:27 +0800 From: Seiya Wang To: Greg Kroah-Hartman , Rob Herring , Matthias Brugger , Daniel Lezcano , Thomas Gleixner CC: , , , , , , Seiya Wang Subject: [PATCH v4 3/3] dt-bindings: timer: Add compatible for Mediatek MT8192 Date: Fri, 14 Aug 2020 14:04:54 +0800 Message-ID: <20200814060454.32200-4-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20200814060454.32200-1-seiya.wang@mediatek.com> References: <20200814060454.32200-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds dt-binding documentation of timer for Mediatek MT8192 SoC Platform. Acked-by: Rob Herring Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 0d256486f886..690a9c0966ac 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -22,6 +22,7 @@ Required properties: For those SoCs that use SYST * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) + * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)