From patchwork Sat Aug 1 04:33:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiyong Tao X-Patchwork-Id: 1339661 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=H1k5P+Wj; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BJWWH6Yd4z9sV4 for ; Sat, 1 Aug 2020 14:34:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725925AbgHAEds (ORCPT ); Sat, 1 Aug 2020 00:33:48 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:20427 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725778AbgHAEds (ORCPT ); Sat, 1 Aug 2020 00:33:48 -0400 X-UUID: d92fb718e37c4de49962c1014af12e93-20200801 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=muT1DKmjGMWq5CVwTCh6Du/qvpKs7a1mFm0DmlPAuNE=; b=H1k5P+WjZEnUQzNNQy9kXEfN3TXXgBhQsOalPbUGDCy9a0wBDDYqQLHT+MygWe1+Rr2dJLYcv+G+p2JqTCS/0rW2Sh1Wffdv3JVRnaEK4jUdaS3p8UcOTIK2+38MLWIxpPltSynh2wl+L0Oj26fM6Se4sh8hreZpZwMpPVw7lJc=; X-UUID: d92fb718e37c4de49962c1014af12e93-20200801 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1021681349; Sat, 01 Aug 2020 12:33:42 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 1 Aug 2020 12:33:39 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 1 Aug 2020 12:33:39 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 2/3] dt-bindings: pinctrl: mt8192: add binding document Date: Sat, 1 Aug 2020 12:33:02 +0800 Message-ID: <20200801043303.32149-3-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200801043303.32149-1-zhiyong.tao@mediatek.com> References: <20200801043303.32149-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: FFA9077AECD97666CD079287376B6B901AD43CEAB38FE06961E2CECE49FC45422000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit adds mt8192 compatible node in binding document. Signed-off-by: Zhiyong Tao --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 175 ++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml new file mode 100755 index 000000000000..88e18e2e23a0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8192 Pin Controller + +maintainers: + - Sean Wang + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: gpio valid number range. + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 11 GPIO + physical address base in mt8192. + maxItems: 11 + + reg-names: + description: | + Gpio base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^pins': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + node { + pinmux = ; + GENERIC_PINCONFIG; + }; + properties: + pinmux: + $ref: "/schemas/types.yaml#/definitions/uint32-array" + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + GENERIC_PINCONFIG: + description: | + It is the generic pinconfig options to use, bias-disable, + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, + output-high, input-schmitt-enable, input-schmitt-disable + and drive-strength are valid. + + Some special pins have extra pull up strength, there are R0 and R1 pull-up + resistors available, but for user, it's only need to set R1R0 as 00, 01, + 10 or 11. So It needs config "mediatek,pull-up-adv" or + "mediatek,pull-down-adv" to support arguments for those special pins. + Valid arguments are from 0 to 3. + + We can use "mediatek,tdsel" which is an integer describing the steps for + output level shifter duty cycle when asserted (high pulse width adjustment). + Valid arguments are from 0 to 15. + We can use "mediatek,rdsel" which is an integer describing the steps for + input level shifter duty cycle when asserted (high pulse width adjustment). + Valid arguments are from 0 to 63. + + When config drive-strength, it can support some arguments, such as + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. + It can only support 2/4/6/8/10/12/14/16mA in mt8192. + For I2C pins, there are existing generic driving setup and the specific + driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving + adjustment in generic driving setup. But in specific driving setup, + they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup for I2C pins, the existing generic driving setup will be + disabled. For some special features, we need the I2C pins specific + driving setup. The specific driving setup is controlled by E1E0EN. + So we need add extra vendor driving preperty instead of + the generic driving property. + We can add "mediatek,drive-strength-adv = ;" to describe the specific + driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1. + It is used to enable or disable the specific driving setup. + E1E0 is used to describe the detail strength specification of the I2C pin. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +examples: + - | + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + };