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[2/4] Documentation: perf: Add documentation for arm-smmu-v3-pmcg

Message ID 20200712163530.61468-1-ajaykumar.rs@samsung.com
State Changes Requested, archived
Headers show
Series None | expand

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Context Check Description
robh/checkpatch warning total: 0 errors, 1 warnings, 21 lines checked

Commit Message

Ajay Kumar July 12, 2020, 4:35 p.m. UTC 
This patch adds devicetree binding for perf/arm_smmuv3_pmu driver.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 .../bindings/perf/arm-smmu-v3-pmcg.txt        | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
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Patch

diff --git a/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
new file mode 100644
index 000000000000..a20fe68ce149
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
@@ -0,0 +1,21 @@ 
+* ARM SMMU V3 PMCG
+
+Required properties:
+
+- compatible: should be "arm-smmu-v3-pmu"
+
+- reg: (standard registers property) physical address and size
+	of the performance counters registers block.
+	If Page 1 is present, specify the same.
+
+- interrupts: (standard interrupt property) single interrupt
+	generated by the SMMU PMU control block
+
+Example:
+
+	pmcg@20002000 {
+		compatible = "arm-smmu-v3-pmu";
+		reg = <0x0 0x20002000 0x0 0x1000>,
+			<0x0 0x20022000 0x0 0xE00>; /* Page 1 */
+		interrupts = <0 181 4>;
+	};