diff mbox series

[RESEND,v2,07/13] dt-bindings: clock: Introduce SM8250 QCOM Graphics clock bindings

Message ID 20200629211725.2592-8-jonathan@marek.ca
State Changes Requested, archived
Headers show
Series Enable GPU for SM8150 and SM8250 | expand

Checks

Context Check Description
robh/checkpatch warning total: 0 errors, 1 warnings, 114 lines checked
robh/dt-meta-schema fail build log

Commit Message

Jonathan Marek June 29, 2020, 9:17 p.m. UTC 
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SM8250 SoCs.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
 include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h

Comments

Rob Herring July 2, 2020, 8:46 p.m. UTC | #1 
On Mon, Jun 29, 2020 at 05:17:13PM -0400, Jonathan Marek wrote:
> Add device tree bindings for graphics clock controller for
> Qualcomm Technology Inc's SM8250 SoCs.
> 

Looks like these 2 schemas could be a single one.

> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
>  include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
> new file mode 100644
> index 000000000000..2b9c8f97b76d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
> +
> +maintainers:
> +  -
> +
> +description: |
> +  Qualcomm graphics clock control module which supports the clocks, resets and
> +  power domains on SM8250.
> +
> +  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
> +
> +properties:
> +  compatible:
> +    const: qcom,sm8250-gpucc
> +
> +  clocks:
> +    items:
> +      - description: Board XO source
> +      - description: GPLL0 main branch source
> +      - description: GPLL0 div branch source
> +
> +  clock-names:
> +    items:
> +      - const: bi_tcxo
> +      - const: gcc_gpu_gpll0_clk_src
> +      - const: gcc_gpu_gpll0_div_clk_src
> +
> +  '#clock-cells':
> +    const: 1
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  '#power-domain-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#reset-cells'
> +  - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
> +    #include <dt-bindings/clock/qcom,rpmh.h>
> +    clock-controller@3d90000 {
> +      compatible = "qcom,sm8250-gpucc";
> +      reg = <0x3d90000 0x9000>;
> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
> +               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +      clock-names = "bi_tcxo",
> +                    "gcc_gpu_gpll0_clk_src",
> +                    "gcc_gpu_gpll0_div_clk_src";
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +      #power-domain-cells = <1>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
> new file mode 100644
> index 000000000000..c8fe64e399fd
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
> +
> +/* GPU_CC clock registers */
> +#define GPU_CC_AHB_CLK				0
> +#define GPU_CC_CRC_AHB_CLK			1
> +#define GPU_CC_CX_APB_CLK			2
> +#define GPU_CC_CX_GMU_CLK			3
> +#define GPU_CC_CX_QDSS_AT_CLK			4
> +#define GPU_CC_CX_QDSS_TRIG_CLK			5
> +#define GPU_CC_CX_QDSS_TSCTR_CLK		6
> +#define GPU_CC_CX_SNOC_DVM_CLK			7
> +#define GPU_CC_CXO_AON_CLK			8
> +#define GPU_CC_CXO_CLK				9
> +#define GPU_CC_GMU_CLK_SRC			10
> +#define GPU_CC_GX_GMU_CLK			11
> +#define GPU_CC_GX_QDSS_TSCTR_CLK		12
> +#define GPU_CC_GX_VSENSE_CLK			13
> +#define GPU_CC_PLL1				14
> +#define GPU_CC_SLEEP_CLK			15
> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
> +
> +/* GPU_CC Resets */
> +#define GPUCC_GPU_CC_ACD_BCR			0
> +#define GPUCC_GPU_CC_CX_BCR			1
> +#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
> +#define GPUCC_GPU_CC_GMU_BCR			3
> +#define GPUCC_GPU_CC_GX_BCR			4
> +#define GPUCC_GPU_CC_XO_BCR			5
> +
> +/* GPU_CC GDSCRs */
> +#define GPU_CX_GDSC				0
> +#define GPU_GX_GDSC				1
> +
> +#endif
> -- 
> 2.26.1
>
Jonathan Marek July 2, 2020, 8:49 p.m. UTC | #2 
On 7/2/20 4:46 PM, Rob Herring wrote:
> On Mon, Jun 29, 2020 at 05:17:13PM -0400, Jonathan Marek wrote:
>> Add device tree bindings for graphics clock controller for
>> Qualcomm Technology Inc's SM8250 SoCs.
>>
> 
> Looks like these 2 schemas could be a single one.
> 

I agree, but there are already separate schemas for sdm845 and sc7180 
gpucc (which these are a copy paste of), so should those be removed and 
use the single one too?

>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>>   .../bindings/clock/qcom,sm8250-gpucc.yaml     | 74 +++++++++++++++++++
>>   include/dt-bindings/clock/qcom,gpucc-sm8250.h | 40 ++++++++++
>>   2 files changed, 114 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>>   create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8250.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>> new file mode 100644
>> index 000000000000..2b9c8f97b76d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
>> @@ -0,0 +1,74 @@
>> +# SPDX-License-Identifier: GPL-2.0-only
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
>> +
>> +maintainers:
>> +  -
>> +
>> +description: |
>> +  Qualcomm graphics clock control module which supports the clocks, resets and
>> +  power domains on SM8250.
>> +
>> +  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,sm8250-gpucc
>> +
>> +  clocks:
>> +    items:
>> +      - description: Board XO source
>> +      - description: GPLL0 main branch source
>> +      - description: GPLL0 div branch source
>> +
>> +  clock-names:
>> +    items:
>> +      - const: bi_tcxo
>> +      - const: gcc_gpu_gpll0_clk_src
>> +      - const: gcc_gpu_gpll0_div_clk_src
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    const: 1
>> +
>> +  '#power-domain-cells':
>> +    const: 1
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - clock-names
>> +  - '#clock-cells'
>> +  - '#reset-cells'
>> +  - '#power-domain-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
>> +    #include <dt-bindings/clock/qcom,rpmh.h>
>> +    clock-controller@3d90000 {
>> +      compatible = "qcom,sm8250-gpucc";
>> +      reg = <0x3d90000 0x9000>;
>> +      clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>> +               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>> +      clock-names = "bi_tcxo",
>> +                    "gcc_gpu_gpll0_clk_src",
>> +                    "gcc_gpu_gpll0_div_clk_src";
>> +      #clock-cells = <1>;
>> +      #reset-cells = <1>;
>> +      #power-domain-cells = <1>;
>> +    };
>> +...
>> diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
>> new file mode 100644
>> index 000000000000..c8fe64e399fd
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
>> @@ -0,0 +1,40 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
>> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
>> +
>> +/* GPU_CC clock registers */
>> +#define GPU_CC_AHB_CLK				0
>> +#define GPU_CC_CRC_AHB_CLK			1
>> +#define GPU_CC_CX_APB_CLK			2
>> +#define GPU_CC_CX_GMU_CLK			3
>> +#define GPU_CC_CX_QDSS_AT_CLK			4
>> +#define GPU_CC_CX_QDSS_TRIG_CLK			5
>> +#define GPU_CC_CX_QDSS_TSCTR_CLK		6
>> +#define GPU_CC_CX_SNOC_DVM_CLK			7
>> +#define GPU_CC_CXO_AON_CLK			8
>> +#define GPU_CC_CXO_CLK				9
>> +#define GPU_CC_GMU_CLK_SRC			10
>> +#define GPU_CC_GX_GMU_CLK			11
>> +#define GPU_CC_GX_QDSS_TSCTR_CLK		12
>> +#define GPU_CC_GX_VSENSE_CLK			13
>> +#define GPU_CC_PLL1				14
>> +#define GPU_CC_SLEEP_CLK			15
>> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
>> +
>> +/* GPU_CC Resets */
>> +#define GPUCC_GPU_CC_ACD_BCR			0
>> +#define GPUCC_GPU_CC_CX_BCR			1
>> +#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
>> +#define GPUCC_GPU_CC_GMU_BCR			3
>> +#define GPUCC_GPU_CC_GX_BCR			4
>> +#define GPUCC_GPU_CC_XO_BCR			5
>> +
>> +/* GPU_CC GDSCRs */
>> +#define GPU_CX_GDSC				0
>> +#define GPU_GX_GDSC				1
>> +
>> +#endif
>> -- 
>> 2.26.1
>>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
new file mode 100644
index 000000000000..2b9c8f97b76d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8250-gpucc.yaml
@@ -0,0 +1,74 @@ 
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8250-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding for SM8250
+
+maintainers:
+  -
+
+description: |
+  Qualcomm graphics clock control module which supports the clocks, resets and
+  power domains on SM8250.
+
+  See also dt-bindings/clock/qcom,gpucc-sm8250.h.
+
+properties:
+  compatible:
+    const: qcom,sm8250-gpucc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source
+      - description: GPLL0 div branch source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: gcc_gpu_gpll0_clk_src
+      - const: gcc_gpu_gpll0_div_clk_src
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@3d90000 {
+      compatible = "qcom,sm8250-gpucc";
+      reg = <0x3d90000 0x9000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+      clock-names = "bi_tcxo",
+                    "gcc_gpu_gpll0_clk_src",
+                    "gcc_gpu_gpll0_div_clk_src";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8250.h b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
new file mode 100644
index 000000000000..c8fe64e399fd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gpucc-sm8250.h
@@ -0,0 +1,40 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H
+
+/* GPU_CC clock registers */
+#define GPU_CC_AHB_CLK				0
+#define GPU_CC_CRC_AHB_CLK			1
+#define GPU_CC_CX_APB_CLK			2
+#define GPU_CC_CX_GMU_CLK			3
+#define GPU_CC_CX_QDSS_AT_CLK			4
+#define GPU_CC_CX_QDSS_TRIG_CLK			5
+#define GPU_CC_CX_QDSS_TSCTR_CLK		6
+#define GPU_CC_CX_SNOC_DVM_CLK			7
+#define GPU_CC_CXO_AON_CLK			8
+#define GPU_CC_CXO_CLK				9
+#define GPU_CC_GMU_CLK_SRC			10
+#define GPU_CC_GX_GMU_CLK			11
+#define GPU_CC_GX_QDSS_TSCTR_CLK		12
+#define GPU_CC_GX_VSENSE_CLK			13
+#define GPU_CC_PLL1				14
+#define GPU_CC_SLEEP_CLK			15
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		16
+
+/* GPU_CC Resets */
+#define GPUCC_GPU_CC_ACD_BCR			0
+#define GPUCC_GPU_CC_CX_BCR			1
+#define GPUCC_GPU_CC_GFX3D_AON_BCR		2
+#define GPUCC_GPU_CC_GMU_BCR			3
+#define GPUCC_GPU_CC_GX_BCR			4
+#define GPUCC_GPU_CC_XO_BCR			5
+
+/* GPU_CC GDSCRs */
+#define GPU_CX_GDSC				0
+#define GPU_GX_GDSC				1
+
+#endif