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[29/38] dt-bindings: tegra: pmc: Increase clock limit for power domains

Message ID 20200612141903.2391044-30-thierry.reding@gmail.com
State Changes Requested
Headers show
Series dt-bindings: json-schema conversions and cleanups | expand

Commit Message

Thierry Reding June 12, 2020, 2:18 p.m. UTC
From: Thierry Reding <treding@nvidia.com>

Power domains (such as the SOR domain) can have more than 8 clocks. Bump
the limit to 10 which is enough as of now.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 81534d04094b..881bfc6154e2 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -213,7 +213,7 @@  properties:
         patternProperties:
           clocks:
             minItems: 1
-            maxItems: 8
+            maxItems: 10
             description:
               Must contain an entry for each clock required by the PMC
               for controlling a power-gate.