| Message ID | 20200611211144.9421-1-luca@lucaceresoli.net |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/5] dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Thu, Jun 11, 2020 at 11:11:40PM +0200, Luca Ceresoli wrote: > The Xilinx 7-series uses the same protocol, mention that. > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Moritz Fischer <mdf@kernel.org> > --- > .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > index cfa4ed42b62f..9f103f3872e8 100644 > --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > @@ -1,11 +1,14 @@ > Xilinx Slave Serial SPI FPGA Manager > > -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over > -what is referred to as "slave serial" interface. > +Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the > +bitstream over what is referred to as "slave serial" interface. > The slave serial link is not technically SPI, and might require extra > circuits in order to play nicely with other SPI slaves on the same bus. > > -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf > +See: > +- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf > +- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf > +- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf > > Required properties: > - compatible: should contain "xlnx,fpga-slave-serial" > -- > 2.27.0 >
Hi Luca, On Thu, Jun 11, 2020 at 11:11:44PM +0200, Luca Ceresoli wrote: > The INIT_B reports the status during startup and after the end of the > programming process. However the current driver completely ignores it. > > Check the pin status during startup to make sure programming is never > started too early and also to detect any hardware issues in the FPGA > connection. > > This is optional for backward compatibility. If INIT_B is not passed by > device tree, just fallback to the old udelays. > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > --- > drivers/fpga/xilinx-spi.c | 54 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 53 insertions(+), 1 deletion(-) > > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > index 799ae04301be..2710a15ed16b 100644 > --- a/drivers/fpga/xilinx-spi.c > +++ b/drivers/fpga/xilinx-spi.c > @@ -23,6 +23,7 @@ > struct xilinx_spi_conf { > struct spi_device *spi; > struct gpio_desc *prog_b; > + struct gpio_desc *init_b; > struct gpio_desc *done; > }; > > @@ -36,11 +37,44 @@ static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) > return FPGA_MGR_STATE_UNKNOWN; > } > > +/** > + * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait > + * a given delay if the pin is unavailable > + * > + * @mgr The FPGA manager object > + * @value Value INIT_B to wait for (1 = asserted = low) > + * @act_udelay Delay to wait if the INIT_B pin is not available > + * > + * Returns 0 when the pin reached the given state or -ETIMEDOUT if too much > + * time passed waiting for that. If there is no INIT_B, always return 0. > + */ > +static int wait_for_init_b(struct fpga_manager *mgr, int value, > + unsigned long backup_udelay) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + unsigned long timeout = jiffies + msecs_to_jiffies(1000); > + > + if (conf->init_b) { > + while (time_before(jiffies, timeout)) { > + /* dump_state(conf, "wait for init_d .."); */ > + if (gpiod_get_value(conf->init_b) == value) > + return 0; > + usleep_range(100, 400); > + } > + return -ETIMEDOUT; > + } > + > + udelay(backup_udelay); > + > + return 0; > +} > + > static int xilinx_spi_write_init(struct fpga_manager *mgr, > struct fpga_image_info *info, > const char *buf, size_t count) > { > struct xilinx_spi_conf *conf = mgr->priv; > + int err; > > if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > @@ -49,10 +83,21 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr, > > gpiod_set_value(conf->prog_b, 1); > > - udelay(1); /* min is 500 ns */ > + err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */ > + if (err) { > + dev_err(&mgr->dev, "INIT_B pin did not go low\n"); > + gpiod_set_value(conf->prog_b, 0); > + return err; > + } > > gpiod_set_value(conf->prog_b, 0); > > + err = wait_for_init_b(mgr, 0, 0); > + if (err) { > + dev_err(&mgr->dev, "INIT_B pin did not go high\n"); > + return err; > + } > + > if (gpiod_get_value(conf->done)) { > dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); > return -EIO; > @@ -154,6 +199,13 @@ static int xilinx_spi_probe(struct spi_device *spi) > return PTR_ERR(conf->prog_b); > } > > + conf->init_b = devm_gpiod_get_optional(&spi->dev, "init_b", GPIOD_IN); > + if (IS_ERR(conf->init_b)) { > + dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n", > + PTR_ERR(conf->init_b)); > + return PTR_ERR(conf->init_b); > + } > + > conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); > if (IS_ERR(conf->done)) { > dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", > -- > 2.27.0 > Series looks good, will apply to for-next. Thanks, Moritz
On Thu, 11 Jun 2020 23:11:40 +0200, Luca Ceresoli wrote: > The Xilinx 7-series uses the same protocol, mention that. > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > --- > .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, Jun 17, 2020 at 04:38:41PM -0600, Rob Herring wrote: > On Thu, 11 Jun 2020 23:11:40 +0200, Luca Ceresoli wrote: > > The Xilinx 7-series uses the same protocol, mention that. > > > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > > --- > > .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > Acked-by: Rob Herring <robh@kernel.org> Applied to for-next, Thanks
On Thu, Jun 11, 2020 at 11:11:41PM +0200, Luca Ceresoli wrote: > The Xilinx 7-series uses the same protocol, mention that. > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > --- > drivers/fpga/xilinx-spi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > index 272ee0c22822..79106626c3f8 100644 > --- a/drivers/fpga/xilinx-spi.c > +++ b/drivers/fpga/xilinx-spi.c > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > - * Xilinx Spartan6 Slave Serial SPI Driver > + * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver > * > * Copyright (C) 2017 DENX Software Engineering > * > -- > 2.27.0 > Applied to for-next, Thanks
On Thu, Jun 11, 2020 at 11:11:42PM +0200, Luca Ceresoli wrote: > Using variables does not add readability here: parameters passed > to udelay*() are obviously in microseconds and their meaning is clear > from the context. > > The type is also wrong, udelay expects an unsigned long. > > Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> > --- > drivers/fpga/xilinx-spi.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > index 79106626c3f8..799ae04301be 100644 > --- a/drivers/fpga/xilinx-spi.c > +++ b/drivers/fpga/xilinx-spi.c > @@ -41,8 +41,6 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr, > const char *buf, size_t count) > { > struct xilinx_spi_conf *conf = mgr->priv; > - const size_t prog_latency_7500us = 7500; > - const size_t prog_pulse_1us = 1; > > if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > @@ -51,7 +49,7 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr, > > gpiod_set_value(conf->prog_b, 1); > > - udelay(prog_pulse_1us); /* min is 500 ns */ > + udelay(1); /* min is 500 ns */ > > gpiod_set_value(conf->prog_b, 0); > > @@ -61,7 +59,7 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr, > } > > /* program latency */ > - usleep_range(prog_latency_7500us, prog_latency_7500us + 100); > + usleep_range(7500, 7600); > return 0; > } > > -- > 2.27.0 > Applied to for-next, Thanks!
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt index cfa4ed42b62f..9f103f3872e8 100644 --- a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt @@ -1,11 +1,14 @@ Xilinx Slave Serial SPI FPGA Manager -Xilinx Spartan-6 FPGAs support a method of loading the bitstream over -what is referred to as "slave serial" interface. +Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the +bitstream over what is referred to as "slave serial" interface. The slave serial link is not technically SPI, and might require extra circuits in order to play nicely with other SPI slaves on the same bus. -See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf +See: +- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf +- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf +- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf Required properties: - compatible: should contain "xlnx,fpga-slave-serial"
The Xilinx 7-series uses the same protocol, mention that. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> --- .../devicetree/bindings/fpga/xilinx-slave-serial.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)