| Message ID | 20200512204543.22090-1-robh@kernel.org |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | [1/5] spi: dt-bindings: sifive: Add missing 2nd register region | expand |
On Tue, 12 May 2020 15:45:39 -0500, Rob Herring wrote: > The 'reg' description and example have a 2nd register region for memory > mapped flash, but the schema says there is only 1 region. Fix this. Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8 Thanks! [1/1] spi: dt-bindings: sifive: Add missing 2nd register region commit: b265b5a0ba15b6e00abce9bf162926e84b4323b4 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
On Wed, May 13, 2020 at 7:10 AM Mark Brown <broonie@kernel.org> wrote: > > On Tue, 12 May 2020 15:45:39 -0500, Rob Herring wrote: > > The 'reg' description and example have a 2nd register region for memory > > mapped flash, but the schema says there is only 1 region. Fix this. > > Applied to > > https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8 > > Thanks! > > [1/1] spi: dt-bindings: sifive: Add missing 2nd register region > commit: b265b5a0ba15b6e00abce9bf162926e84b4323b4 You missed my ask for an ack. This is a dependency for patch 5. Rob
On Wed, May 13, 2020 at 08:02:14AM -0500, Rob Herring wrote: > On Wed, May 13, 2020 at 7:10 AM Mark Brown <broonie@kernel.org> wrote: > > [1/1] spi: dt-bindings: sifive: Add missing 2nd register region > > commit: b265b5a0ba15b6e00abce9bf162926e84b4323b4 > You missed my ask for an ack. This is a dependency for patch 5. Ah, there was no cover letter. Acked-by: Mark Brown <broonie@kernel.org>
On Tue, 12 May 2020, Rob Herring wrote: > The 'reg' description and example have a 2nd register region for memory > mapped flash, but the schema says there is only 1 region. Fix this. > > Cc: Mark Brown <broonie@kernel.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Paul Walmsley <paul.walmsley@sifive.com> > Cc: linux-spi@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Signed-off-by: Rob Herring <robh@kernel.org> > --- > Please ack, dependency for patch 5. Acked-by: Paul Walmsley <paul.walmsley@sifive.com> - Paul
diff --git a/Documentation/devicetree/bindings/spi/spi-sifive.yaml b/Documentation/devicetree/bindings/spi/spi-sifive.yaml index 28040598bfae..fb583e57c1f2 100644 --- a/Documentation/devicetree/bindings/spi/spi-sifive.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sifive.yaml @@ -32,11 +32,10 @@ properties: https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi reg: - maxItems: 1 - - description: - Physical base address and size of SPI registers map - A second (optional) range can indicate memory mapped flash + minItems: 1 + items: + - description: SPI registers region + - description: Memory mapped flash region interrupts: maxItems: 1
The 'reg' description and example have a 2nd register region for memory mapped flash, but the schema says there is only 1 region. Fix this. Cc: Mark Brown <broonie@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: linux-spi@vger.kernel.org Cc: linux-riscv@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> --- Please ack, dependency for patch 5. Documentation/devicetree/bindings/spi/spi-sifive.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)