| Message ID | 20200304072730.9193-4-zhang.lyra@gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add clocks for Unisoc's SC9863A | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | "total: 0 errors, 1 warnings, 105 lines checked" |
| robh/dt-meta-schema | success |
Hi Rob, Can I have your acked-by on this patch now? Or do you have comments? Thanks, Chunyan On Wed, 4 Mar 2020 at 15:28, Chunyan Zhang <zhang.lyra@gmail.com> wrote: > > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > add a new bindings to describe sc9863a clock compatible string. > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > --- > .../bindings/clock/sprd,sc9863a-clk.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml > > diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml > new file mode 100644 > index 000000000000..bb3a78d8105e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright 2019 Unisoc Inc. > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: SC9863A Clock Control Unit Device Tree Bindings > + > +maintainers: > + - Orson Zhai <orsonzhai@gmail.com> > + - Baolin Wang <baolin.wang7@gmail.com> > + - Chunyan Zhang <zhang.lyra@gmail.com> > + > +properties: > + "#clock-cells": > + const: 1 > + > + compatible : > + enum: > + - sprd,sc9863a-ap-clk > + - sprd,sc9863a-aon-clk > + - sprd,sc9863a-apahb-gate > + - sprd,sc9863a-pmu-gate > + - sprd,sc9863a-aonapb-gate > + - sprd,sc9863a-pll > + - sprd,sc9863a-mpll > + - sprd,sc9863a-rpll > + - sprd,sc9863a-dpll > + - sprd,sc9863a-mm-gate > + - sprd,sc9863a-apapb-gate > + > + clocks: > + minItems: 1 > + maxItems: 4 > + description: | > + The input parent clock(s) phandle for this clock, only list fixed > + clocks which are declared in devicetree. > + > + clock-names: > + minItems: 1 > + maxItems: 4 > + items: > + - const: ext-26m > + - const: ext-32k > + - const: ext-4m > + - const: rco-100m > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - '#clock-cells' > + > +if: > + properties: > + compatible: > + enum: > + - sprd,sc9863a-ap-clk > + - sprd,sc9863a-aon-clk > +then: > + required: > + - reg > + > +else: > + description: | > + Other SC9863a clock nodes should be the child of a syscon node in > + which compatible string shoule be: > + "sprd,sc9863a-glbregs", "syscon", "simple-mfd" > + > + The 'reg' property for the clock node is also required if there is a sub > + range of registers for the clocks. > + > +examples: > + - | > + ap_clk: clock-controller@21500000 { > + compatible = "sprd,sc9863a-ap-clk"; > + reg = <0 0x21500000 0 0x1000>; > + clocks = <&ext_26m>, <&ext_32k>; > + clock-names = "ext-26m", "ext-32k"; > + #clock-cells = <1>; > + }; > + > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ap_ahb_regs: syscon@20e00000 { > + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; > + reg = <0 0x20e00000 0 0x4000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x20e00000 0x4000>; > + > + apahb_gate: apahb-gate@0 { > + compatible = "sprd,sc9863a-apahb-gate"; > + reg = <0x0 0x1020>; > + #clock-cells = <1>; > + }; > + }; > + }; > + > +... > -- > 2.20.1 >
On Wed, 4 Mar 2020 15:27:26 +0800, Chunyan Zhang wrote: > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > add a new bindings to describe sc9863a clock compatible string. > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > --- > .../bindings/clock/sprd,sc9863a-clk.yaml | 105 ++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
Quoting Chunyan Zhang (2020-03-03 23:27:26) > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > add a new bindings to describe sc9863a clock compatible string. > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> [...] > +examples: > + - | > + ap_clk: clock-controller@21500000 { > + compatible = "sprd,sc9863a-ap-clk"; > + reg = <0 0x21500000 0 0x1000>; > + clocks = <&ext_26m>, <&ext_32k>; > + clock-names = "ext-26m", "ext-32k"; > + #clock-cells = <1>; > + }; > + > + - | > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ap_ahb_regs: syscon@20e00000 { > + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; > + reg = <0 0x20e00000 0 0x4000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0x20e00000 0x4000>; > + > + apahb_gate: apahb-gate@0 { Why do we need a node per "clk type" in the simple-mfd syscon? Can't we register clks from the driver that matches the parent node and have that driver know what sorts of clks are where? Sorry I haven't read the rest of the patch series and I'm not aware if this came up before. If so, please put details about this in the commit text. > + compatible = "sprd,sc9863a-apahb-gate"; > + reg = <0x0 0x1020>; > + #clock-cells = <1>;
Hi Stephen, On Sat, 21 Mar 2020 at 09:12, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Chunyan Zhang (2020-03-03 23:27:26) > > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > > > add a new bindings to describe sc9863a clock compatible string. > > > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > [...] > > +examples: > > + - | > > + ap_clk: clock-controller@21500000 { > > + compatible = "sprd,sc9863a-ap-clk"; > > + reg = <0 0x21500000 0 0x1000>; > > + clocks = <&ext_26m>, <&ext_32k>; > > + clock-names = "ext-26m", "ext-32k"; > > + #clock-cells = <1>; > > + }; > > + > > + - | > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + ap_ahb_regs: syscon@20e00000 { > > + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; > > + reg = <0 0x20e00000 0 0x4000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0 0x20e00000 0x4000>; > > + > > + apahb_gate: apahb-gate@0 { > > Why do we need a node per "clk type" in the simple-mfd syscon? Can't we > register clks from the driver that matches the parent node and have that > driver know what sorts of clks are where? Sorry I haven't read the rest > of the patch series and I'm not aware if this came up before. If so, > please put details about this in the commit text. Please see the change logs after v2 in cover-letter. Rob suggested us to put some clocks under syscon nodes, since these clocks have the same physical address base with the syscon; Thanks, Chunyan > > > + compatible = "sprd,sc9863a-apahb-gate"; > > + reg = <0x0 0x1020>; > > + #clock-cells = <1>;
Quoting Chunyan Zhang (2020-03-22 04:00:39) > Hi Stephen, > > On Sat, 21 Mar 2020 at 09:12, Stephen Boyd <sboyd@kernel.org> wrote: > > > > Quoting Chunyan Zhang (2020-03-03 23:27:26) > > > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > > > > > add a new bindings to describe sc9863a clock compatible string. > > > > > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > > [...] > > > +examples: > > > + - | > > > + ap_clk: clock-controller@21500000 { > > > + compatible = "sprd,sc9863a-ap-clk"; > > > + reg = <0 0x21500000 0 0x1000>; > > > + clocks = <&ext_26m>, <&ext_32k>; > > > + clock-names = "ext-26m", "ext-32k"; > > > + #clock-cells = <1>; > > > + }; > > > + > > > + - | > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + > > > + ap_ahb_regs: syscon@20e00000 { > > > + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; > > > + reg = <0 0x20e00000 0 0x4000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + ranges = <0 0 0x20e00000 0x4000>; > > > + > > > + apahb_gate: apahb-gate@0 { > > > > Why do we need a node per "clk type" in the simple-mfd syscon? Can't we > > register clks from the driver that matches the parent node and have that > > driver know what sorts of clks are where? Sorry I haven't read the rest > > of the patch series and I'm not aware if this came up before. If so, > > please put details about this in the commit text. > > Please see the change logs after v2 in cover-letter. > > Rob suggested us to put some clocks under syscon nodes, since these > clocks have the same > physical address base with the syscon; Ok. I'll apply the series to clk-next then.
On Wed, 25 Mar 2020 at 10:03, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Chunyan Zhang (2020-03-22 04:00:39) > > Hi Stephen, > > > > On Sat, 21 Mar 2020 at 09:12, Stephen Boyd <sboyd@kernel.org> wrote: > > > > > > Quoting Chunyan Zhang (2020-03-03 23:27:26) > > > > From: Chunyan Zhang <chunyan.zhang@unisoc.com> > > > > > > > > add a new bindings to describe sc9863a clock compatible string. > > > > > > > > Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> > > > [...] > > > > +examples: > > > > + - | > > > > + ap_clk: clock-controller@21500000 { > > > > + compatible = "sprd,sc9863a-ap-clk"; > > > > + reg = <0 0x21500000 0 0x1000>; > > > > + clocks = <&ext_26m>, <&ext_32k>; > > > > + clock-names = "ext-26m", "ext-32k"; > > > > + #clock-cells = <1>; > > > > + }; > > > > + > > > > + - | > > > > + soc { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + > > > > + ap_ahb_regs: syscon@20e00000 { > > > > + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; > > > > + reg = <0 0x20e00000 0 0x4000>; > > > > + #address-cells = <1>; > > > > + #size-cells = <1>; > > > > + ranges = <0 0 0x20e00000 0x4000>; > > > > + > > > > + apahb_gate: apahb-gate@0 { > > > > > > Why do we need a node per "clk type" in the simple-mfd syscon? Can't we > > > register clks from the driver that matches the parent node and have that > > > driver know what sorts of clks are where? Sorry I haven't read the rest > > > of the patch series and I'm not aware if this came up before. If so, > > > please put details about this in the commit text. > > > > Please see the change logs after v2 in cover-letter. > > > > Rob suggested us to put some clocks under syscon nodes, since these > > clocks have the same > > physical address base with the syscon; > > Ok. I'll apply the series to clk-next then. Thank you. Chunyan
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml new file mode 100644 index 000000000000..bb3a78d8105e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019 Unisoc Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: SC9863A Clock Control Unit Device Tree Bindings + +maintainers: + - Orson Zhai <orsonzhai@gmail.com> + - Baolin Wang <baolin.wang7@gmail.com> + - Chunyan Zhang <zhang.lyra@gmail.com> + +properties: + "#clock-cells": + const: 1 + + compatible : + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk + - sprd,sc9863a-apahb-gate + - sprd,sc9863a-pmu-gate + - sprd,sc9863a-aonapb-gate + - sprd,sc9863a-pll + - sprd,sc9863a-mpll + - sprd,sc9863a-rpll + - sprd,sc9863a-dpll + - sprd,sc9863a-mm-gate + - sprd,sc9863a-apapb-gate + + clocks: + minItems: 1 + maxItems: 4 + description: | + The input parent clock(s) phandle for this clock, only list fixed + clocks which are declared in devicetree. + + clock-names: + minItems: 1 + maxItems: 4 + items: + - const: ext-26m + - const: ext-32k + - const: ext-4m + - const: rco-100m + + reg: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + +if: + properties: + compatible: + enum: + - sprd,sc9863a-ap-clk + - sprd,sc9863a-aon-clk +then: + required: + - reg + +else: + description: | + Other SC9863a clock nodes should be the child of a syscon node in + which compatible string shoule be: + "sprd,sc9863a-glbregs", "syscon", "simple-mfd" + + The 'reg' property for the clock node is also required if there is a sub + range of registers for the clocks. + +examples: + - | + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0 0x21500000 0 0x1000>; + clocks = <&ext_26m>, <&ext_32k>; + clock-names = "ext-26m", "ext-32k"; + #clock-cells = <1>; + }; + + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + ap_ahb_regs: syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; + reg = <0 0x20e00000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate@0 { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + }; + +...