From patchwork Mon Nov 18 15:25:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Ratiu X-Patchwork-Id: 1196821 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47Gt7W1KTlz9sRf for ; Tue, 19 Nov 2019 02:25:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727310AbfKRPZL (ORCPT ); Mon, 18 Nov 2019 10:25:11 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:56774 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727306AbfKRPZK (ORCPT ); Mon, 18 Nov 2019 10:25:10 -0500 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: aratiu) with ESMTPSA id 9907428E105 From: Adrian Ratiu To: linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-imx@nxp.com, Sjoerd Simons , Martyn Welch Subject: [PATCH v3 4/4] dt-bindings: display: add IMX MIPI DSI host controller doc Date: Mon, 18 Nov 2019 17:25:18 +0200 Message-Id: <20191118152518.3374263-5-adrian.ratiu@collabora.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191118152518.3374263-1-adrian.ratiu@collabora.com> References: <20191118152518.3374263-1-adrian.ratiu@collabora.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Sjoerd Simons Signed-off-by: Martyn Welch Signed-off-by: Adrian Ratiu --- .../bindings/display/imx/mipi-dsi.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt diff --git a/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt new file mode 100644 index 000000000000..3f05c32ef963 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt @@ -0,0 +1,56 @@ +Freescale i.MX6 DW MIPI DSI Host Controller +=========================================== + +The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP +with a companion PHY IP. + +These DT bindings follow the Synopsys DW MIPI DSI bindings defined in +Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with +the following device-specific properties. + +Required properties: + +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. +- compatible: "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi". +- reg: See dw_mipi_dsi.txt. +- interrupts: The controller's CPU interrupt. +- clocks, clock-names: Phandles to the controller's pll reference + clock(ref) and APB clock(pclk), as described in [1]. +- ports: a port node with endpoint definitions as defined in [2]. +- gpr: Should be <&gpr>. + Phandle to the iomuxc-gpr region containing the multiplexer + control register. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + + mipi_dsi: mipi@21e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x021e0000 0x4000>; + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, + <&clks IMX6QDL_CLK_MIPI_IPG>; + clock-names = "ref", "pclk"; + status = "okay"; + + ports { + port@0 { + reg = <0>; + mipi_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_mipi>; + }; + }; + port@1 { + reg = <1>; + mipi_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_mipi>; + }; + }; + }; + };