From patchwork Wed Mar 20 23:48:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1059634 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="NNtx2zb2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44PmpJ6yngz9sR0 for ; Thu, 21 Mar 2019 10:48:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727667AbfCTXsR (ORCPT ); Wed, 20 Mar 2019 19:48:17 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:11921 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727478AbfCTXsP (ORCPT ); Wed, 20 Mar 2019 19:48:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1553125695; x=1584661695; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8+GS09e2kuxAm41XWJLYt8y5cTm3Ai/BqW043K5L6o4=; b=NNtx2zb2y9sGKLKamKklGu9AuMQxKk1aHQcoehX4jkMUmlBZ2ld56Kr6 +N5Bdukf3Zn5sWosocu6aSfgL92pzXz//WvFEBwU02BBDqDcBzRP3vs6w NG+NQPNplcFLn3EPb/Vo6K4htTJz7lUS4nPsBS8aXB5Yxuk31JGc0Vw57 Rr3VrtTixrNPjxfO7vK/DLEDXIBUSZzyCwofwOHnyuoV0f5IuWFSk3tJu 8POwAdk6FFzGAgdZ49DBIPJO6/x/akuoiSmGUJC0A3XnvDZUQIuNeKPlP n1HrmVG/Vy7QDcsNEIRjRe+DxNqO8KzF2bRVCpJquapY1AEFRDICqCZep w==; X-IronPort-AV: E=Sophos;i="5.60,250,1549900800"; d="scan'208";a="103874316" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 21 Mar 2019 07:48:15 +0800 IronPort-SDR: mxqfAq8Ke2yMkXI5FRXQPXJBIcL0SUIHpB9TfLOEYe8JvOh7ZuL0gLI2XGm4nlF2JOv1Fa2kGh 49FoFhvBpOObNHHfWXKmL9oY5x7Nki9HM3yV+D0eS0I60ZoGEHSztlkl2u1dmcxRB5/oGbMg0b 4fCQz9a8ZE8gaVkjwv7pZ38hDKo8B0fnQ6bf6sqtRs3DUeRB3TzynvAvUUysztxi7z0kQBNo7w FvQsuACdW6eV/a/wp/wKB2MpWRFjQIDpkRWkdCxXXKvI1MmgdyTB80KUtZYpiPvtDDClwa5O8F goK1ovJudsY5p+vdDb9vmrxq Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 20 Mar 2019 16:27:52 -0700 IronPort-SDR: Lzd9zrpBxuvOxN6UBKKq8X/tVYNVlG7Ll9jP+kayjJZ+zTZmiDXWlHXB7ErYVYouYINWVkqXWn E1ME3G9uZnXmVc+ibzLqXuJye1s8omY9roT4jxZ+VWbm1/TmtWTd5vlnMI3B9bXrSJhpgrNbtS Mf47+JOWvDzu1PRfMLkDf1PuYMv/29duqltRdzxXpH1M4oZ3ioD0Rv5JppuJTzBUuekZ8FvF5C YEUBQ/MgqO8vJsO0M/fp41GlMZXwwTEqQ0fs1tTGx2b1EFU6EqiDyQSCt6tZFkc5j2KbtbPmuG I08= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 20 Mar 2019 16:48:15 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Sudeep Holla , Albert Ou , Anup Patel , Ard Biesheuvel , Catalin Marinas , devicetree@vger.kernel.org, Dmitriy Cherkasov , Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , Johan Hovold , linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Will Deacon Subject: [RFT/RFC PATCH v3 2/5] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Wed, 20 Mar 2019 16:48:03 -0700 Message-Id: <20190320234806.19748-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190320234806.19748-1-atish.patra@wdc.com> References: <20190320234806.19748-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla Reviewed-by: Rob Herring --- .../topology.txt => cpu/cpu-topology.txt} | 82 +++++++++++++++---- 1 file changed, 66 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 3b8febb4..069addcc 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,31 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The cpu nodes, as per bindings defined in [4], represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [4] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +489,63 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +{ + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU1>; + }; + core1 { + cpu = <&CPU2>; + }; + core2 { + cpu0 = <&CPU2>; + }; + core3 { + cpu0 = <&CPU3>; + }; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/