From patchwork Sat Feb 23 13:07:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 1047379 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="xXkMle++"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4467nB25d4z9sB3 for ; Sun, 24 Feb 2019 00:08:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725893AbfBWNI2 (ORCPT ); Sat, 23 Feb 2019 08:08:28 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:36818 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728049AbfBWNI2 (ORCPT ); Sat, 23 Feb 2019 08:08:28 -0500 Received: by mail-wr1-f68.google.com with SMTP id o17so5209298wrw.3 for ; Sat, 23 Feb 2019 05:08:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W2dxKE8aR3SbsBUnOM8VJ3TaIyns8oX/QNEJc6UdJd4=; b=xXkMle++srbgR6rDFndB/M/frNLCtDQ/O8ZZlGKk53o80qYsHfjw8Cw25Lr9R4Ny/q X49i3aGtr1veA2cfKvdYPGkx3JyeXAceQrVpiEAWUlbUTMMvtv7CeolsWYbGlqcrjIGb 5Yh6xOB1zk6eQPJMc4vT3PGFDMS6areYrrXTjryEMyNRR4jzQDBoGYV2fYVkkQHorL/b odtLcPndmMko74Q9/IS4LKWEhUATgA3kb8Fzg5e2leCSpoRjzpXtLoJCbYnMQ7RreyVd 3zUU0EqCDAkMQA3nOj1NPsMecrPWQFm/6fxMz/1mz1EwNR1TlDZc7RhKoSYNdCHhLX9I EvPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W2dxKE8aR3SbsBUnOM8VJ3TaIyns8oX/QNEJc6UdJd4=; b=ffc2bgQ/oBd/cIgjHqMYIvpLtuWyzl4TnZv509qe9kuKTiMdc0FNF8cNGUBI4c0SaU i2Ij9LjrwQ4laEXYZ0vSNST41xpcGfqg3TSTKFSX52o3wqmhDR36YFDvsTXII7f2u/ZG hmTA3mYZP3z+YO+qPRPnWTdbhAszOh9y1RR3/6ibF3HMKZ6EcMEVMcH3GA395JpVX+nR 5EI2UmYxHw3MA6rMNUU3UEJzSHRCOSZQflh3LP4/R+ASSG8yfScmDO7ytPXoqTgcH3A3 VTFi5L20e3MZ0JTYrsG/SvBDxVm0cllAZEhkM2/MrPmMKify76MCChL2Czrqop+80Eh0 eZ1Q== X-Gm-Message-State: AHQUAuY5VUgjDbofL+m3fKAS2XcMh3VXb3KUMlRFfu6WgbywUkBO8mrL /w81DVc+9B8HblcvAawP/CLtGA== X-Google-Smtp-Source: AHgI3IZsCdtvtPISsSQGT/JOdp6hMDEbuDGCqxhkyNQ6MmLVq6Tkwr9Jc2rUZksa2rrJz9O5MLKCQA== X-Received: by 2002:adf:9d85:: with SMTP id p5mr6427328wre.215.1550927306073; Sat, 23 Feb 2019 05:08:26 -0800 (PST) Received: from clegane.local (189.126.130.77.rev.sfr.net. [77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:25 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Joseph Lo , devicetree@vger.kernel.org, Jon Hunter , Rob Herring , Mark Rutland , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 16/18] dt-bindings: timer: add Tegra210 timer Date: Sat, 23 Feb 2019 14:07:04 +0100 Message-Id: <20190223130707.16704-16-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Joseph Lo The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring Acked-by: Jon Hunter Signed-off-by: Daniel Lezcano --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +};