From patchwork Thu Dec 13 09:34:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012701 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="MQFGEqGh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpS30C9Yz9s6w for ; Thu, 13 Dec 2018 20:34:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeLMJe6 (ORCPT ); Thu, 13 Dec 2018 04:34:58 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1326 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJe5 (ORCPT ); Thu, 13 Dec 2018 04:34:57 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:53 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:57 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:34:57 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:56 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:56 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:56 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH V2 03/21] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Date: Thu, 13 Dec 2018 17:34:20 +0800 Message-ID: <20181213093438.29621-4-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693693; bh=q0UMDemwz5MCXWMdMFgDi5JSy2ea57JJxHGTiEJ/RfE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=MQFGEqGhEVeAXndVNGRcj0VKidCRV7QkRlHCGKB4giT/+tbflnHuTJSFmXf2XmO8J 6XGO/0xCU6CldBP12AB+dWm0zbjoH394T8D1KlypIuRbQMlHbUqdoLcLwPf2l7mQdS jBa8nlNgNHTcWc5DKO7KM3d5ZiBAUY76ArRgC3OtU+g9S4vnzRlhs+omyL9dRHXrUo MFVR3wTGkzHlC+VEN5J0WyzhjlfVnFKr3A8FS4LoUlYrk4Jt1fKH/SKepTHtVd4ew0 kTEbWl9OAJo3ml+41CzfFYFlmGHH73G9fjboWOwIS12IFkPmZvmYAf5lmvUM5l+vsl lDkPVXvtvguCw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V2: - add ack tag --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..031545a29caf 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -13,7 +13,6 @@ Required properties: - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -37,7 +36,6 @@ cpus { <&dfll>; clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...>