From patchwork Tue May 1 16:12:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 907099 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=csie.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40b62T00X7z9s2t for ; Wed, 2 May 2018 02:15:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755942AbeEAQPZ (ORCPT ); Tue, 1 May 2018 12:15:25 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:37406 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755912AbeEAQPX (ORCPT ); Tue, 1 May 2018 12:15:23 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id 4C5FD5FDEA; Wed, 2 May 2018 00:15:17 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Michael Turquette , Stephen Boyd , Giuseppe Cavallaro , Rob Herring , Mark Rutland , Mark Brown Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, Corentin Labbe , Icenowy Zheng Subject: [PATCH net-next v2 06/15] dt-bindings: net: dwmac-sun8i: Add binding for GMAC on Allwinner R40 SoC Date: Wed, 2 May 2018 00:12:18 +0800 Message-Id: <20180501161227.2110-7-wens@csie.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501161227.2110-1-wens@csie.org> References: <20180501161227.2110-1-wens@csie.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner R40 SoC has the EMAC controller supported by dwmac-sun8i. It is named "GMAC", while EMAC refers to the 10/100 Mbps Ethernet controller supported by sun4i-emac. The controller is the same, but the R40 has the glue layer controls in the clock control unit (CCU), with a reduced RX delay chain, and no TX delay chain. This patch adds the R40 specific bits to the dwmac-sun8i binding. Signed-off-by: Chen-Yu Tsai Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 1c0906a5c02b..cfe724398a12 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -7,6 +7,7 @@ Required properties: - compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" + "allwinner,sun8i-r40-gmac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. @@ -25,8 +26,10 @@ Required properties: Optional properties: - allwinner,tx-delay-ps: TX clock delay chain value in ps. Range is 0-700. Default is 0. + Unavailable for allwinner,sun8i-r40-gmac - allwinner,rx-delay-ps: RX clock delay chain value in ps. Range is 0-3100. Default is 0. + Range is 0-700 for allwinner,sun8i-r40-gmac Both delay properties need to be a multiple of 100. They control the clock delay for external RGMII PHY. They do not apply to the internal PHY or external non-RGMII PHYs.