From patchwork Sat Apr 21 13:55:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 902446 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40SvQ60QLHz9s1w for ; Sat, 21 Apr 2018 23:55:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752786AbeDUNz4 (ORCPT ); Sat, 21 Apr 2018 09:55:56 -0400 Received: from mail.bootlin.com ([62.4.15.54]:58685 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752700AbeDUNzz (ORCPT ); Sat, 21 Apr 2018 09:55:55 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id DD0AA208A8; Sat, 21 Apr 2018 15:55:53 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (unknown [91.224.148.103]) by mail.bootlin.com (Postfix) with ESMTPSA id D20AF2081A; Sat, 21 Apr 2018 15:55:52 +0200 (CEST) From: Miquel Raynal To: Thomas Gleixner , Jason Cooper , Marc Zyngier Cc: Catalin Marinas , Will Deacon , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Maxime Chevallier , Nadav Haklai , Haim Boot , Hanna Hawa , Miquel Raynal Subject: [PATCH 14/17] dt-bindings/interrupt-controller: add description for Marvell SEI node Date: Sat, 21 Apr 2018 15:55:34 +0200 Message-Id: <20180421135537.24716-15-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180421135537.24716-1-miquel.raynal@bootlin.com> References: <20180421135537.24716-1-miquel.raynal@bootlin.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe the SEI (System Error Interrupt) controller driver. The controller is part of the GIC. It aggregates two types of interrupts, wired and MSIs from respectively the AP and the CPs, into a single SPI interrupt. Suggested-by: Haim Boot Signed-off-by: Miquel Raynal --- .../bindings/interrupt-controller/marvell,sei.txt | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt new file mode 100644 index 000000000000..a246d59552b1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt @@ -0,0 +1,54 @@ +Marvell SEI (System Error Interrupt) Controller +----------------------------------------------- + +Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. +It receives interrupts from several sources and aggregates them to a single +interrupt line (an SPI) on the primary interrupt controller. + +The IRQ chip can handle up to 64 SEIs, a set comes from the AP and is +wired while a second set comes from the CPs by the mean of MSIs. Each +'domain' is represented as a subnode. + +Required properties: + +- compatible: should be "marvell,armada-8k-sei". +- reg: SEI registers location and length. +- interrupts: identifies the parent IRQ that will be triggered. +- #address-cells: should be '1', represents the position of the first + IRQ of a given type in the SEI range. +- #size-cells: should be '1', represents the number of a given type of + IRQs. + +Child node 'sei-wired-controller' required properties: + +- reg: the range of wired interrupts. +- #interrupt-cells: number of cells to define an SEI wired interrupt + coming from the AP, should be 1. The cell is the IRQ + number. +- interrupt-controller: identifies the node as an interrupt controller. + +Child node 'sei-msi-controller' required properties: + +- reg: the range of non-wired interrupts triggered by way of MSIs. +- msi-controller: identifies the node as an MSI controller. + +Example: + + sei: sei@3f0200 { + compatible = "marvell,armada-8k-sei"; + reg = <0x3f0200 0x40>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + + sei_wired_controller: sei-wired-controller@0 { + reg = <0 21>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + sei_msi_controller: sei-msi-controller@21 { + reg = <21 43>; + msi-controller; + }; + };