From patchwork Thu Feb 8 15:20:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 870906 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zchjn0B0cz9s82 for ; Fri, 9 Feb 2018 02:21:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752021AbeBHPVQ (ORCPT ); Thu, 8 Feb 2018 10:21:16 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:47460 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750929AbeBHPUt (ORCPT ); Thu, 8 Feb 2018 10:20:49 -0500 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 8C239272754 From: Enric Balletbo i Serra To: Rob Herring , Kishon Vijay Abraham I , Brian Norris Cc: Heiko Stuebner , dianders@chromium.org, Chris Zhong , William wu , hl@rock-chips.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH 2/3] Documentation: bindings: add usb3-host-disable and usb3-host-port for Rockchip USB Type-C PHY Date: Thu, 8 Feb 2018 16:20:27 +0100 Message-Id: <20180208152028.9997-2-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208152028.9997-1-enric.balletbo@collabora.com> References: <20180208152028.9997-1-enric.balletbo@collabora.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: William wu rockchip,usb3-host-disable is the register of type-c phy disable usb3 host rockchip,usb3-host-port is the register of type-c phy usb3 port number Signed-off-by: William wu Signed-off-by: Enric Balletbo i Serra --- Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt index c3be83be9615..9085d95d0079 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -36,6 +36,12 @@ offset, enable bit, write mask bit. - rockchip,uphy-dp-sel : the register of type-c phy enable DP function for type-c phy0, it must be <0x6268 19 19>; for type-c phy1, it must be <0x6268 3 19>; + - rockchip,usb3-host-disable : the register of type-c phy disable usb3 host + for type-c phy0, it must be <0x2434 0 16>; + for type-c phy1, it must be <0x2444 0 16>; + - rockchip,usb3-host-port : the register of type-c phy usb3 port number + for type-c phy0, it must be <0x2434 12 28>; + for type-c phy1, it must be <0x2444 12 28>; Required nodes : a sub-node is required for each port the phy provides. The sub-node name is used to identify dp or usb3 port,