| Message ID | 20171219094540.18432-2-kishon@ti.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | ti-pipe3: PCIe x2 lane mode configuration in dra72 | expand |
On Tue, Dec 19, 2017 at 03:15:39PM +0530, Kishon Vijay Abraham I wrote: > DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property > to indicate if the USB3 PHY should be used for 2nd lane of PCIe. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt > index cd13e6157088..907a046e794b 100644 > --- a/Documentation/devicetree/bindings/phy/ti-phy.txt > +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt > @@ -93,6 +93,8 @@ Optional properties: > register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. > - syscon-pcs : phandle/offset pair. Phandle to the system control module and the > register offset to write the PCS delay value. > + - "ti,configure-as-pcie" : property to indicate if the PHY should be > + configured as PCIE PHY. This is not that uncommon as PCIe, 10Gb eth, USB3, SATA are all very electrically similar and the same phy can drive all of them AIUI. The DT already contains the necessary information too because you have a phys property creating a link to PCI host. The problem is either the client side would need to set the mode or you'd have to search all "phys" properties to find the link. There's already a DT function to iterate thru all named properties. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index cd13e6157088..907a046e794b 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -93,6 +93,8 @@ Optional properties: register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. - syscon-pcs : phandle/offset pair. Phandle to the system control module and the register offset to write the PCS delay value. + - "ti,configure-as-pcie" : property to indicate if the PHY should be + configured as PCIE PHY. Deprecated properties: - ctrl-module : phandle of the control module used by PHY driver to power on
DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property to indicate if the USB3 PHY should be used for 2nd lane of PCIe. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++ 1 file changed, 2 insertions(+)