From patchwork Sun Sep 10 06:49:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 812043 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="a9Y9i2Pq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xqhXG1YLWz9sQl for ; Sun, 10 Sep 2017 16:50:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751082AbdIJGuX (ORCPT ); Sun, 10 Sep 2017 02:50:23 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:32912 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751193AbdIJGuV (ORCPT ); Sun, 10 Sep 2017 02:50:21 -0400 Received: by mail-pf0-f195.google.com with SMTP id h4so3517719pfk.0; Sat, 09 Sep 2017 23:50:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jr45JsYVW9J+7yojqvYAWBitWBvMilmAd6Yr+njD+kg=; b=a9Y9i2PqovDc4VkoOcQWCwESmXVqRLzUbZEDht+WIJd6BqDcQmgkC9cwIGJjY+CRBy avD27zjJuJogsvwqHTzVV6N2t3MX4KRUO/uLy58E3ElK0TkCgTuHyvBW4NQWzKYBJY8F DrFxunp+x6nIrx8hbQSv+pisCToLf6pkThzT82mTibripyHo37BHjm8Ocs7MknF/2zkH 0PqrfnA2FmhKKCAAuQrG8VtlDZ/l6T7wwWPfLFikxTMjFvnCsDL/1zDPTzD/X6/a3d5P iG9Xd5TWKaooOOlxbAcTwjsJXL2frIHRBQmYMfxD6pmDbEGrUiluBhWzOemn1gU6ckxg IcXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jr45JsYVW9J+7yojqvYAWBitWBvMilmAd6Yr+njD+kg=; b=JuQEeCTDeTmEARKRpGZFv3TrprqDR725Ff5yEjKYu3qlOlkviwgglT4uSnO3PTR0Ec RaLhzhFzCrOu0iuJdU2Wq7JBXCSgSgVrdd1SNWlAH0LJ+dQrGvTw4oBi9QorOlsJhHQ5 UO/RxzI+mf9sfXXOeHFCiERRinbGQ0Jm9OXGqVqKGpMnUd7ULOuIhXf0mytFWvpqVSzn VCHrolphYNyJW2AgVdtQ/r+B8OUFuivRseXZH+s1Pfmh2XD3y+wcWhaPIKQBHSpfKEEM 704DNdfOW+cJq11WZN9ewiYq6WNdpqwUT4SnJso5Wm7BQC6xA4xORC8eAvY2MAx4lATl /DgA== X-Gm-Message-State: AHPjjUhH3+ThsQEJmuwJNGqWVSIHJvwoMqoEva7tzR2dG7VmR2tqLJdi Az0bPjmOhRcZDSbrGI7Y7w== X-Google-Smtp-Source: ADKCNb5Dwxd1ij94GowYvFdYX1NvpQFmXAqyzrC2MAKJ8SnEMUCBMhixJYH2kA+2u8FQYoM9sEkimQ== X-Received: by 10.84.129.68 with SMTP id 62mr9487077plb.186.1505026220100; Sat, 09 Sep 2017 23:50:20 -0700 (PDT) Received: from localhost (g186.58-98-166.ppp.wakwak.ne.jp. [58.98.166.186]) by smtp.gmail.com with ESMTPSA id v186sm9737878pfb.51.2017.09.09.23.50.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Sep 2017 23:50:19 -0700 (PDT) From: Stafford Horne To: LKML Cc: Openrisc , Stefan Kristiansson , Stafford Horne , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Jonas Bonn , devicetree@vger.kernel.org Subject: [PATCH v2 06/14] irqchip: add initial support for ompic Date: Sun, 10 Sep 2017 15:49:18 +0900 Message-Id: <20170910064926.5874-7-shorne@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910064926.5874-1-shorne@gmail.com> References: <20170910064926.5874-1-shorne@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Stefan Kristiansson IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multicore support section of the OpenRISC 1.2 proposed architecture specification: https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC. Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation. Signed-off-by: Stefan Kristiansson [shorne@gmail.com: converted ops to bitmask, wrote commit message] Signed-off-by: Stafford Horne --- Changes since v1 - Added openrisc, prefix - Clarified 8 bytes per cpu - Removed #interrupt-cells as this will not be an irq parent - Changed ops to be percpu - Added DTS and intialization failure validations .../interrupt-controller/openrisc,ompic.txt | 19 ++ arch/openrisc/Kconfig | 1 + drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ompic.c | 205 +++++++++++++++++++++ 5 files changed, 229 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt create mode 100644 drivers/irqchip/irq-ompic.c diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt new file mode 100644 index 000000000000..346e6042d62f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt @@ -0,0 +1,19 @@ +Open Multi-Processor Interrupt Controller + +Required properties: + +- compatible : This should be "openrisc,ompic" +- reg : Specifies base physical address and size of the register space. The + size is based on the number of cores the controller has been configured + to handle, this should be set to 8 bytes per cpu core. +- interrupt-controller : Identifies the node as an interrupt controller +- interrupts : Specifies the interrupt line to which the ompic is wired. + +Example: + +ompic: ompic { + compatible = "openrisc,ompic"; + reg = <0x98000000 16>; + interrupt-controller; + interrupts = <1>; +}; diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index b49acda5e8f4..34eb4e90f56c 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -30,6 +30,7 @@ config OPENRISC select NO_BOOTMEM select ARCH_USE_QUEUED_SPINLOCKS select ARCH_USE_QUEUED_RWLOCKS + select OMPIC if SMP config CPU_BIG_ENDIAN def_bool y diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f1fd5f44d1d4..0e4c96c90b86 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP select SPARSE_IRQ default y +config OMPIC + bool + config OR1K_PIC bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e88d856cc09c..123047d7a20d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o +obj-$(CONFIG_OMPIC) += irq-ompic.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c new file mode 100644 index 000000000000..cd2616b6639b --- /dev/null +++ b/drivers/irqchip/irq-ompic.c @@ -0,0 +1,205 @@ +/* + * Open Multi-Processor Interrupt Controller driver + * + * Copyright (C) 2014 Stefan Kristiansson + * Copyright (C) 2017 Stafford Horne + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + * + * The ompic device handles IPI communication because cores in mulicore + * OpenRISC systems. + * + * Registers + * + * For each CPU the ompic has 2 registers. The control register for sending + * and acking IPIs and the status register for receiving IPIs. The register + * layouts are as follows: + * + * Control register + * +---------+---------+----------+---------+ + * | 31 | 30 | 29 .. 16 | 15 .. 0 | + * ----------+---------+----------+---------- + * | IRQ ACK | IRQ GEN | DST CORE | DATA | + * +---------+---------+----------+---------+ + * + * Status register + * +----------+-------------+----------+---------+ + * | 31 | 30 | 29 .. 16 | 15 .. 0 | + * -----------+-------------+----------+---------+ + * | Reserved | IRQ Pending | SRC CORE | DATA | + * +----------+-------------+----------+---------+ + * + * Architecture + * + * - The ompic generates a level interrupt to the CPU PIC when a message is + * ready. Messages are delivered via the memory bus. + * - The ompic does not have any interrupt input lines. + * - The ompic is wired to the same irq line on each core. + * - Devices are wired to the same irq line on each core. + * + * +---------+ +---------+ + * | CPU | | CPU | + * | Core 0 |<==\ (memory access) /==>| Core 1 | + * | [ PIC ]| | | | [ PIC ]| + * +----^-^--+ | | +----^-^--+ + * | | v v | | + * <====|=|=================================|=|==> (memory bus) + * | | ^ ^ | | + * (ipi | +------|---------+--------|-------|-+ (device irq) + * irq | | | | | + * core0)| +------|---------|--------|-------+ (ipi irq core1) + * | | | | | + * +----o-o-+ | +--------+ | + * | ompic |<===/ | Device |<===/ + * | IPI | +--------+ + * +--------+* + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OMPIC_CPUBYTES 8 +#define OMPIC_CTRL(cpu) (0x0 + (cpu * OMPIC_CPUBYTES)) +#define OMPIC_STAT(cpu) (0x4 + (cpu * OMPIC_CPUBYTES)) + +#define OMPIC_CTRL_IRQ_ACK (1 << 31) +#define OMPIC_CTRL_IRQ_GEN (1 << 30) +#define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16) + +#define OMPIC_STAT_IRQ_PENDING (1 << 30) + +#define OMPIC_DATA(x) ((x) & 0xffff) + +DEFINE_PER_CPU(unsigned long, ops); + +static void __iomem *ompic_base; + +static inline u32 ompic_readreg(void __iomem *base, loff_t offset) +{ + return ioread32be(base + offset); +} + +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data) +{ + iowrite32be(data, base + offset); +} + +void ompic_raise_softirq(const struct cpumask *mask, unsigned int ipi_msg) +{ + unsigned int dst_cpu; + unsigned int src_cpu = smp_processor_id(); + + for_each_cpu(dst_cpu, mask) { + set_bit(ipi_msg, &per_cpu(ops, dst_cpu)); + + /* + * On OpenRISC the atomic set_bit() call implies a memory + * barrier. Otherwise we would need: smp_wmb(); paired + * with the read in ompic_ipi_handler. + */ + + ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu), + OMPIC_CTRL_IRQ_GEN | + OMPIC_CTRL_DST(dst_cpu) | + OMPIC_DATA(1)); + } +} + +irqreturn_t ompic_ipi_handler(int irq, void *dev_id) +{ + unsigned int cpu = smp_processor_id(); + unsigned long *pending_ops = &per_cpu(ops, cpu); + unsigned long ops; + + ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK); + while ((ops = xchg(pending_ops, 0)) != 0) { + + /* + * On OpenRISC the atomic xchg() call implies a memory + * barrier. Otherwise we may need an smp_rmb(); paired + * with the write in ompic_raise_softirq. + */ + + do { + unsigned long ipi_msg; + + ipi_msg = __ffs(ops); + ops &= ~(1UL << ipi_msg); + + handle_IPI(ipi_msg); + } while (ops); + } + + return IRQ_HANDLED; +} + +static struct irqaction ompi_ipi_irqaction = { + .handler = ompic_ipi_handler, + .flags = IRQF_PERCPU, + .name = "ompic_ipi", +}; + +int __init ompic_of_init(struct device_node *node, struct device_node *parent) +{ + struct resource res; + int irq; + int ret; + + /* Validate the DT */ + if (ompic_base) { + pr_err("ompic: duplicate ompic's are not supported"); + return -EEXIST; + } + + if (of_address_to_resource(node, 0, &res)) { + pr_err("ompic: reg property requires an address and size"); + return -EINVAL; + } + + if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) { + pr_err("ompic: reg size, currently %d must be at least %d", + resource_size(&res), + (num_possible_cpus() * OMPIC_CPUBYTES)); + return -EINVAL; + } + + /* Setup the device */ + ompic_base = ioremap(res.start, resource_size(&res)); + if (IS_ERR(ompic_base)) { + pr_err("ompic: unable to map registers"); + return PTR_ERR(ompic_base); + } + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) { + pr_err("ompic: unable to parse device irq"); + ret = -EINVAL; + goto out_unmap; + } + + ret = setup_irq(irq, &ompi_ipi_irqaction); + if (ret) + goto out_irq_disp; + + set_smp_cross_call(ompic_raise_softirq); + + return 0; + +out_irq_disp: + irq_dispose_mapping(irq); +out_unmap: + iounmap(ompic_base); + ompic_base = NULL; + return ret; +} +IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);