From patchwork Thu May 25 17:29:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Clayton X-Patchwork-Id: 767062 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wYbqg5QJMz9s7g for ; Fri, 26 May 2017 03:29:51 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ma+xBhqb"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424817AbdEYR3p (ORCPT ); Thu, 25 May 2017 13:29:45 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35081 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1424790AbdEYR3X (ORCPT ); Thu, 25 May 2017 13:29:23 -0400 Received: by mail-pf0-f193.google.com with SMTP id u26so40542322pfd.2; Thu, 25 May 2017 10:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ydYg4FUlppwM7ARApLWfPLTunY/Q4yZXQMHaQbRQw8Y=; b=Ma+xBhqbZi2AFklhuNJGihtO3YwkoaUidUkB3uXuYbPmHonySr5JniOiFi+WhurfhA ZKgxWjQPVN/95BvRc7FEiVBPj33qMluBJSfO2IsgXggxuO/Si4Zp9z0AIOtMF2SraOEP lDWHvjN4ywcE993VdjwuADgD5z8SU3+JlJ5/BvksvvGh/l+4pLchoBRKSJpOtXjnu277 7NsvSFv/+I5U98jdJlFdelVs9VaBYq1V81QegQSmeHCOPT+xPd4zXQtXcUweBpgDbEDT vttc/tYY1zrINdDHsYk8mixR5kCg0LoCaqLvdQINxBbABaYmH94f9xbS/ZJ17h8RoVo6 pybw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ydYg4FUlppwM7ARApLWfPLTunY/Q4yZXQMHaQbRQw8Y=; b=BkzAyBZHAm7CmoHUnNxOEwlp/82wbGaycT0vbpMygZ3+pQ8e1oD3eVAMBPiokY+aaj D8klWQyPms6RUdRPuYRY2Wo78HZWWkOrMbUje2HvpRHEEqenkLVaz8nLLKl8UtgKIlSf deo0R1JAIagzbCNMkBQLGhusDGUpMGtNQ4UpZr9/MolZ3rp36yOZPMFLtFyIb0OyaJjl hryCpfLGNFPIByXguXPhiZ5ekQqIvxy1aTxkWztbhN4tAbeNYTrmw/ipOKy96iWIZ3b+ 1TtkX4uKYDWVbnoqWQUvX7yt5ZkesKHgQt+DXkjmBY6/0ic9DUHth0AZFYhRrNafp9zu XI4A== X-Gm-Message-State: AODbwcBoyz5Mne5lJo5813z4z0nh05oJR4gGINDlblLvPG3v1jGTJ2LR P35OdUARTQWJsQ== X-Received: by 10.99.123.70 with SMTP id k6mr45902521pgn.135.1495733362285; Thu, 25 May 2017 10:29:22 -0700 (PDT) Received: from localhost.localdomain (68-185-59-186.static.knwc.wa.charter.com. [68.185.59.186]) by smtp.gmail.com with ESMTPSA id b72sm16579738pfj.36.2017.05.25.10.29.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 May 2017 10:29:21 -0700 (PDT) From: Joshua Clayton To: Alan Tull , Moritz Fischer , Anatolij Gustschin , Bastian Stender , Shawn Guo , Joshua Clayton Cc: Rob Herring , Mark Rutland , Sascha Hauer , Fabio Estevam , Russell King , linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v11 2/6] doc: dt: add altera-ps-spi binding document Date: Thu, 25 May 2017 10:29:07 -0700 Message-Id: <20170525172911.11467-3-stillcompiling@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170525172911.11467-1-stillcompiling@gmail.com> References: <20170525172911.11467-1-stillcompiling@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe an altera-ps-spi devicetree entry, required features Signed-off-by: Joshua Clayton Acked-by: Rob Herring Signed-off-by: Anatolij Gustschin --- .../bindings/fpga/altera-passive-serial.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt new file mode 100644 index 000000000000..3e240b281f21 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt @@ -0,0 +1,29 @@ +Altera Passive Serial SPI FPGA Manager + +Altera FPGAs support a method of loading the bitstream over what is +referred to as "passive serial". +The passive serial link is not technically SPI, and might require extra +circuits in order to play nicely with other SPI slaves on the same bus. + +See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf + +Required properties: +- compatible: Must be one of the following: + "altr,fpga-passive-serial", + "altr,fpga-arria10-passive-serial" +- reg: SPI chip select of the FPGA +- nconfig-gpios: config pin (referred to as nCONFIG in the manual) +- nstat-gpios: status pin (referred to as nSTATUS in the manual) + +Optional properties: +- confd-gpios: confd pin (referred to as CONF_DONE in the manual) + +Example: + fpga_spi: evi-fpga-spi@0 { + compatible = "altr,fpga-passive-serial"; + spi-max-frequency = <20000000>; + reg = <0>; + nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + };