From patchwork Wed Mar 29 19:46:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 744977 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vth8S0Lyfz9s2Q for ; Thu, 30 Mar 2017 08:43:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932201AbdC2Tsv (ORCPT ); Wed, 29 Mar 2017 15:48:51 -0400 Received: from hermes.aosc.io ([172.82.152.187]:45316 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932181AbdC2TsY (ORCPT ); Wed, 29 Mar 2017 15:48:24 -0400 Received: from localhost.localdomain (unknown [120.236.174.154]) (Authenticated sender: icenowy@aosc.io) by hermes.aosc.io (Postfix) with ESMTPSA id 654D27E722; Wed, 29 Mar 2017 19:48:14 +0000 (UTC) From: Icenowy Zheng To: Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com, Icenowy Zheng Subject: [PATCH v3 03/11] dt-bindings: add bindings for DE2 on V3s SoC Date: Thu, 30 Mar 2017 03:46:05 +0800 Message-Id: <20170329194613.55548-4-icenowy@aosc.io> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170329194613.55548-1-icenowy@aosc.io> References: <20170329194613.55548-1-icenowy@aosc.io> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Icenowy Zheng Allwinner V3s SoC have a display engine which have a different pipeline with older SoCs. Add document for it (new compatibles and the new "mixer" part). The paragraph of TCON is also refactored, for furtherly add TCONs in A83T/H3/A64/H5 that have only a channel 1 (used for HDMI or TV Encoder). Signed-off-by: Icenowy Zheng --- Changes in v3: - Remove the description of having a BE directly as allwinner,pipeline. .../bindings/display/sunxi/sun4i-drm.txt | 37 +++++++++++++++++++--- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index b82c00449468..38de5e96f359 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -31,11 +31,11 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon + * allwinner,sun8i-v3s-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - - clocks: phandles to the clocks feeding the TCON. Three are needed: + - clocks: phandles to the clocks feeding the TCON - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0 - resets: phandles to the reset controllers driving the encoder - "lcd": the reset line for the TCON channel 0 @@ -52,7 +52,12 @@ Required properties: second the block connected to the TCON channel 1 (usually the TV encoder) -On SoCs other than the A33, there is one more clock required: +On TCONs that have a channel 0 (currently all TCONs supported), there +is one more clock required: + - 'tcon-ch0': The clock driving the TCON channel 0 + +On TCONs that have a channel 1 (currently all TCONs except the ones in +A33 and V3s), there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC @@ -137,6 +142,26 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoints, the second one the outputs +Display Engine 2.0 Mixer +------------------------ + +The DE2 mixer have many functionalities, currently only layer blending is +supported. + +Required properties: + - compatible: value must be one of: + * allwinner,sun8i-v3s-de2-mixer + - reg: base address and size of the memory-mapped region. + - clocks: phandles to the clocks feeding the frontend and backend + * bus: the backend interface clock + * ram: the backend DRAM clock + - clock-names: the clock names mentioned above + - resets: phandles to the reset controllers driving the backend + +- ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port should be the input endpoints, the second one the output + Display Engine Pipeline ----------------------- @@ -151,9 +176,13 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine + * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine - frontends available. + pipeline entry point. For SoCs with original DE (currently + all SoCs supported by display engine except V3s), this + phandle should be a display frontend; for SoCs with DE2, + this phandle should be a mixer. Example: