From patchwork Wed Feb 22 16:31:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 731206 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vT2vL5xlcz9s7k for ; Thu, 23 Feb 2017 03:31:58 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ClaWhqA9"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932578AbdBVQbv (ORCPT ); Wed, 22 Feb 2017 11:31:51 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:35030 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932960AbdBVQbq (ORCPT ); Wed, 22 Feb 2017 11:31:46 -0500 Received: by mail-wr0-f194.google.com with SMTP id q39so1015572wrb.2 for ; Wed, 22 Feb 2017 08:31:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=OMilCyI/oqajhrNu6zQgq3hNcs8Uol+1YZdxtDOCFC4=; b=ClaWhqA9SLewxet/LedimiWA89Qen7dckGlcfPpf6XdHU7HIMkUvWDrYhGnXs6++td kSxOSS8fGW9N8EjZCUMKr6D7sOslZImUM2v142PA2JdiRNn1PxG3rtfRoBlnkVYm0KCe f5LRV8s32lvHfajSGE49Ec9b4swovn97zz6ezaVGzUhhukCr//uPHMc29llYnJhoXqbW yBC4uPPwFvyCOW51MyM5yt7wJL6fVhyuyVcphdD9mPavT5VIugP0d+G9q3G1viq98t3X 8eigY33sdENlCRlfladDDYT+XktZhpdXoDdvYFT5zvQm1Vr/UocxZqQ9/n0wF91kzQ1J TQ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=OMilCyI/oqajhrNu6zQgq3hNcs8Uol+1YZdxtDOCFC4=; b=RVnLHOvzIj4hAKTxCfrq8igSFfEhtNKm4TynoCJk0u8yvY+ma8/9BX2r2LW/+2HbrO GJ8bqCyfgYrzNa8M0NqPOEcDOLHsica+h32f84k9xctLbVMDGNP4AJLjzXrxU9fsYwIm DRXuR10f+/1azr5fFtMps8kXwlDrfq4dIgirN2uOnnzTlU+eTFqkY41dWYlVoL5cXfXo DRgcQH+oMSa0x6375S8uP0kiq4AqCVfSXV8AhTZz9NFwnhmVlxPvv5M7R4Qn5gWp1pPI HSZMh8lTjMkEEqAErNAjbYz8bfOuMaXd64FZ36iJtQ9QUkCsvZ/OeUV1XX8ML6wdPbVA +/8Q== X-Gm-Message-State: AMke39kKRXpuBgzK3jMlh6lXzMQrQflWZRcj7OKeT3nWETTNdNjV+6Jupb6QisDK6Rpc7A== X-Received: by 10.223.146.2 with SMTP id 2mr13040819wrj.85.1487781099902; Wed, 22 Feb 2017 08:31:39 -0800 (PST) Received: from localhost.localdomain (host44-97-dynamic.48-82-r.retail.telecomitalia.it. [82.48.97.44]) by smtp.gmail.com with ESMTPSA id q12sm3172713wmd.8.2017.02.22.08.31.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Feb 2017 08:31:39 -0800 (PST) From: Carlo Caione To: robh+dt@kernel.org, khilman@baylibre.com, narmstrong@baylibre.com, afaerber@suse.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux@endlessm.com Cc: Carlo Caione Subject: [PATCH 2/2] ARM64: dts: meson-gxl: Add support for HwaCom AmazeTV Date: Wed, 22 Feb 2017 17:31:31 +0100 Message-Id: <20170222163131.14136-3-carlo@caione.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170222163131.14136-1-carlo@caione.org> References: <20170222163131.14136-1-carlo@caione.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Carlo Caione This patch adds support for the HwaCom AmazeTV set-top-box. The hardware configuration is really similar to the other GXL boards but for this hardware we need to limit the max-frequency of the eMMC to have it working. Signed-off-by: Carlo Caione Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxl-hwacom-amazetv.dts | 164 +++++++++++++++++++++ 3 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-hwacom-amazetv.dts diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 9b2b41a..c369a55 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -47,3 +47,4 @@ Board compatible values: - "amlogic,q201" (Meson gxm s912) - "nexbox,a95x" (Meson gxbb or Meson gxl s905x) - "nexbox,a1" (Meson gxm s912) + - "hwacom,amazetv" (Meson gxl s905x) diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0d7bfbf..2932755 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-hwacom-amazetv.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-hwacom-amazetv.dts new file mode 100644 index 0000000..9a2c60d --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-hwacom-amazetv.dts @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2017 Carlo Caione + * Copyright (c) 2016 BayLibre, Inc. + * Author: Neil Armstrong + * + * SPDX-License-Identifier: GPL-2.0+ OR MIT + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "hwacom,amazetv", "amlogic,s905x", "amlogic,meson-gxl"; + model = "Hwacom AmazeTV (S905X)"; + + aliases { + serial0 = &uart_AO; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_card: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "VDDIO_CARD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_card>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "clkin0"; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +};