From patchwork Tue Jan 24 04:05:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Bur X-Patchwork-Id: 718874 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v6vmJ062Vz9sxN for ; Tue, 24 Jan 2017 15:08:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750703AbdAXEHs (ORCPT ); Mon, 23 Jan 2017 23:07:48 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:57265 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750709AbdAXEHs (ORCPT ); Mon, 23 Jan 2017 23:07:48 -0500 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v0O45D2L134648 for ; Mon, 23 Jan 2017 23:07:47 -0500 Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) by mx0a-001b2d01.pphosted.com with ESMTP id 285jtup6ek-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 23 Jan 2017 23:07:46 -0500 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 24 Jan 2017 14:07:41 +1000 Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 2BBA32CE8046 for ; Tue, 24 Jan 2017 15:07:41 +1100 (EST) Received: from d23av06.au.ibm.com (d23av06.au.ibm.com [9.190.235.151]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v0O47Xre26280138 for ; Tue, 24 Jan 2017 15:07:41 +1100 Received: from d23av06.au.ibm.com (localhost [127.0.0.1]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v0O478hB006146 for ; Tue, 24 Jan 2017 15:07:08 +1100 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v0O478G3005549; Tue, 24 Jan 2017 15:07:08 +1100 Received: from camb691.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 2EA00A0237; Tue, 24 Jan 2017 15:06:44 +1100 (AEDT) From: Cyril Bur To: devicetree@vger.kernel.org Cc: robh+dt@kernel.org, joel@jms.id.au, andrew@aj.id.au Subject: [PATCH v2 2/2] Documentation: dt: misc: Add Aspeed ast2400/2500 LPC Control bindings Date: Tue, 24 Jan 2017 15:05:33 +1100 X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170124040533.9144-1-cyrilbur@gmail.com> References: <20170124040533.9144-1-cyrilbur@gmail.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17012404-0004-0000-0000-000001D85B88 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17012404-0005-0000-0000-0000098BCB05 Message-Id: <20170124040533.9144-2-cyrilbur@gmail.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-24_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701240040 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Cyril Bur Acked-by: Rob Herring --- V2: s/ASpeed/Aspeed/ Removed incorrect compatible property from the example Dropped: "This does not have to be the case, provided the reg property can give the full address of the mbox registers." from the "Device Node" section .../devicetree/bindings/misc/aspeed-lpc-ctrl.txt | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/aspeed-lpc-ctrl.txt diff --git a/Documentation/devicetree/bindings/misc/aspeed-lpc-ctrl.txt b/Documentation/devicetree/bindings/misc/aspeed-lpc-ctrl.txt new file mode 100644 index 000000000000..bb5cdd7fb583 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/aspeed-lpc-ctrl.txt @@ -0,0 +1,76 @@ +Aspeed LPC Control +================== +This binding defines the LPC control for Aspeed SoCs. Partitions of +the LPC bus can be access by other processors on the system, address +ranges on the bus can map accesses from another processor to regions +of the Aspeed SoC memory space. + +Reserved Memory: +================ +The driver provides functionality to map the LPC bus to a region of +Aspeed ram. A phandle to a reserved memory node must be provided so +that the driver can safely use this region. + +Flash: +====== +The driver provides functionality to unmap the LPC bus from Aspeed +RAM, historically the default mapping has been to the SPI flash +controller on the Aspeed SoC, a phandle to this node should be +supplied. + +Device Node: +============ + +As LPC bus configuration registers are at the start of the LPC bus +memory space, it makes most sense for the device to be within the LPC +host node. See Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +for more information. + +Required properties: +-------------------- + +- compatible: "aspeed,ast2400-lpc-ctrl" for Aspeed ast2400 SoCs + "aspeed,ast2500-lpc-ctrl" for Aspeed ast2500 SoCs + +- reg: Location and size of the configuration registers + for the LPC bus. Note that if the device node is + within the LPC host node then base is relative to + that. + +- memory-region: phandle of the reserved memory region +- flash: phandle of the SPI flash controller + +Example: +-------- + +reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ... + + flash_memory: region@54000000 { + no-map; + reg = <0x54000000 0x04000000>; /* 64M */ + }; +}; + +host_pnor: spi@1e630000 { + reg = < 0x1e630000 0x18 + 0x30000000 0x02000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2400-smc"; + + ... + +}; + +lpc-ctrl@0 { + compatible = "aspeed,ast2400-lpc-ctrl"; + memory-region = <&flash_memory>; + flash = <&host_pnor>; + reg = <0x0 0x80>; +}; +