From patchwork Sat Jan 21 03:06:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Brandt X-Patchwork-Id: 718002 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v52Y70h3Tz9snk for ; Sat, 21 Jan 2017 14:06:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752661AbdAUDGr (ORCPT ); Fri, 20 Jan 2017 22:06:47 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:24863 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752638AbdAUDGq (ORCPT ); Fri, 20 Jan 2017 22:06:46 -0500 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie3.idc.renesas.com with ESMTP; 21 Jan 2017 12:06:42 +0900 Received: from relmlac4.idc.renesas.com (relmlac4.idc.renesas.com [10.200.69.24]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id BD9354F0DD; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: by relmlac4.idc.renesas.com (Postfix, from userid 0) id BE2A3480A5; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: from relmlac4.idc.renesas.com (localhost [127.0.0.1]) by relmlac4.idc.renesas.com (Postfix) with ESMTP id B60B748014; Sat, 21 Jan 2017 12:06:42 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac4.idc.renesas.com with ESMTP id NAA03540; Sat, 21 Jan 2017 12:06:42 +0900 X-IronPort-AV: E=Sophos;i="5.33,261,1477926000"; d="scan'208";a="231355043" Received: from unknown (HELO rtamta01.rta.renesas.com) ([143.103.48.75]) by relmlii1.idc.renesas.com with ESMTP; 21 Jan 2017 12:06:41 +0900 Received: from localhost.localdomain (unknown [143.103.58.132]) by rtamta01.rta.renesas.com (Postfix) with ESMTP id 48811333; Sat, 21 Jan 2017 03:06:37 +0000 (UTC) From: Chris Brandt To: Ulf Hansson , Rob Herring , Mark Rutland , Simon Horman , Wolfram Sang , Geert Uytterhoeven Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Brandt Subject: [PATCH v5 2/3] mmc: sh_mobile_sdhi: explain clock bindings Date: Fri, 20 Jan 2017 22:06:03 -0500 Message-Id: <20170121030604.7672-3-chris.brandt@renesas.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20170121030604.7672-1-chris.brandt@renesas.com> References: <20170121030604.7672-1-chris.brandt@renesas.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In the case of a single clock source, you don't need names. However, if the controller has 2 clock sources, you need to name them correctly so the driver can find the 2nd one. The 2nd clock is for the internal card detect logic. Signed-off-by: Chris Brandt Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven --- v4: * just explain there might be 2 clocks, don't explain how we will use them in the driver v3: * add more clarification about why there are sometimes 2 clocks and what you should do with them. * remove 'status = "disabled"' from example v2: * fix spelling and change wording * changed clock name from "carddetect" to "cd" --- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index a1650ed..1464c16 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt @@ -25,8 +25,32 @@ Required properties: "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC +- clocks: Most controllers only have 1 clock source per channel. However, on + some variations of this controller, the internal card detection + logic that exists in this controller is sectioned off to be run by a + separate second clock source to allow the main core clock to be turned + off to save power. + If 2 clocks are specified by the hardware, you must name them as + "core" and "cd". + If the controller only has 1 clock, naming is not required. + Optional properties: - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable - pinctrl-names: should be "default", "state_uhs" - pinctrl-0: should contain default/high speed pin ctrl - pinctrl-1: should contain uhs mode pin ctrl + +Example showing 2 clocks: + sdhi0: sd@e804e000 { + compatible = "renesas,sdhi-r7s72100"; + reg = <0xe804e000 0x100>; + interrupts = ; + + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; + cap-sd-highspeed; + cap-sdio-irq; + };