From patchwork Fri Aug 19 12:44:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 660848 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sG2ll5114z9t0M for ; Fri, 19 Aug 2016 22:46:43 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=aj.id.au header.i=@aj.id.au header.b=SJrwY9Zu; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b=O25PU1nS; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754940AbcHSMqm (ORCPT ); Fri, 19 Aug 2016 08:46:42 -0400 Received: from out2-smtp.messagingengine.com ([66.111.4.26]:48868 "EHLO out2-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754948AbcHSMou (ORCPT ); Fri, 19 Aug 2016 08:44:50 -0400 Received: from compute7.internal (compute7.nyi.internal [10.202.2.47]) by mailout.nyi.internal (Postfix) with ESMTP id 69C50205B1; Fri, 19 Aug 2016 08:44:49 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute7.internal (MEProxy); Fri, 19 Aug 2016 08:44:49 -0400 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-sasl-enc:x-sasl-enc; s=mesmtp; bh=t1nRNxdfZcOMFO23WCiuFJ/W1M8 =; b=SJrwY9ZukgqFr10hu/8/Y5n/n3JSs8O/Rtz0RauCmNZcyiVZI3HKBTPzgK6 oPrnN472MCJasw02qRv2pFNsmdZiRDp3+kEEtZVDz8Pijq7HCC2ond6iJApjlwBU qQr00EtqkQpCCCAgvkg84uMyKVKakNunHwW86iWQCiOtInRI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-sasl-enc:x-sasl-enc; s=smtpout; bh=t1nR NxdfZcOMFO23WCiuFJ/W1M8=; b=O25PU1nSOLpWYhtJkcNQlTq/L6Wm1cLL/0mA ZU31gloWQorxk8TZLbexbQV6Jaj/pVmpH/91WlJzpGEM7KzbIlctrPrIctzHoVNY /gU+y1CCOtVbPPT9KPdfHXKrvODD7sEFJl3l4t8PAyvv60AqsHSH1YpNmsyzLoeG MKHdn7c= X-Sasl-enc: iT37d3nsIIypzo5WSZhc563EOPZco4Mmem9lYC800xNC 1471610688 Received: from keelia.au.ibm.com (ppp203-122-213-247.static.internode.on.net [203.122.213.247]) by mail.messagingengine.com (Postfix) with ESMTPA id 33B96CCD84; Fri, 19 Aug 2016 08:44:43 -0400 (EDT) From: Andrew Jeffery To: Linus Walleij , Joel Stanley Cc: Alexandre Courbot , Mark Rutland , Rob Herring , Benjamin Herrenschmidt , Jeremy Kerr , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Andrew Jeffery Subject: [PATCH v2 3/8] pinctrl: dt-bindings: Add documentation for Aspeed pin controllers Date: Fri, 19 Aug 2016 22:14:09 +0930 Message-Id: <20160819124414.24242-4-andrew@aj.id.au> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160819124414.24242-1-andrew@aj.id.au> References: <20160819124414.24242-1-andrew@aj.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Outline expectations on the pin controller's relationship with the System Control Unit (SCU) IP through syscon, and document the compatible strings for 4th and 5th generation Aspeed SoC pin controllers. Signed-off-by: Andrew Jeffery Acked-by: Rob Herring Acked-by: Joel Stanley --- Since v1: * Add SoC-specific compatible strings * Document available function and group property values .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt new file mode 100644 index 000000000000..bfd81be4383b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt @@ -0,0 +1,65 @@ +Aspeed Pin Controllers +---------------------- + +The Aspeed SoCs vary in functionality inside a generation but have a common mux +device register layout. + +Required properties: +- compatible : Should be any one of the following: + "aspeed,ast2400-pinctrl" + "aspeed,g4-pinctrl" + "aspeed,ast2500-pinctrl" + "aspeed,g5-pinctrl" + +The pin controller node should be a child of a syscon node with the required +property: +- compatible: "syscon", "simple-mfd" + +Refer to the the bindings described in +Documentation/devicetree/bindings/mfd/syscon.txt + +Subnode Format +-------------- + +The required properties of child nodes are (as defined in pinctrl-bindings): +- function +- groups + +Each function has only one associated pin group. Each group is named by its +function. The following values for the function and groups properties are +supported: + +aspeed,ast2400-pinctrl, aspeed,g4-pinctrl: + +ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 +I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1 +MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3 +NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16 +ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3 +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30 +VPO12 VPO24 + +aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: + +GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 +I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 +RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 + +Examples: + +syscon: scu@1e6e2000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl@1e6e2000 { + compatible = "aspeed,g4-pinctrl"; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + }; +}; + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices.