diff mbox

[04/24] Documentation: DT bindings: add more chip compatible strings for Tegra timers

Message ID 20150128234937.20644.54294.stgit@dusk.lan
State New, archived
Headers show

Commit Message

Paul Walmsley Jan. 28, 2015, 11:49 p.m. UTC
Add compatible strings for the timer IP blocks present on several
Tegra chips.  The primary objective here is to avoid checkpatch
warnings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: devicetree@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 .../bindings/timer/nvidia,tegra30-timer.txt        |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)



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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index b5082a1cf461..bbf38d26605b 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -6,7 +6,9 @@  trigger a legacy watchdog reset.
 
 Required properties:
 
-- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
+- compatible : "nvidia,tegra30-timer"
+  "nvidia,tegra124-timer" (not yet matched in the driver)
+  "nvidia,tegra132-timer" (not yet matched in the driver)
 - reg : Specifies base physical address and size of the registers.
 - interrupts : A list of 6 interrupts; one per each of timer channels 1
     through 5, and one for the shared interrupt for the remaining channels.