| Message ID | 1700213336-652-2-git-send-email-srinivas.goud@amd.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | can: xilinx_can: Add ECC feature support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Fri, Nov 17, 2023 at 02:58:54PM +0530, Srinivas Goud wrote: > ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of > Xilinx AXI CAN Controller. > Part of this feature configuration and counter registers added in "ECC is an IP configuration option where counter registers are added..." The sentence is hard to parse for the important bit of information - the justification for this being a property rather than based on compatible or autodetectable based on some IP version etc. Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > IP for 1bit/2bit ECC errors. > > 'xlnx,has-ecc' is optional property and added to Xilinx AXI CAN Controller > node if ECC block enabled in the HW > > Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> > --- > Changes in v5: > Update property description > > Changes in v4: > Fix binding check warning > Update property description > > Changes in v3: > Update commit description > > Changes in v2: > None > > Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > index 64d57c3..8d4e5af 100644 > --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > @@ -49,6 +49,10 @@ properties: > resets: > maxItems: 1 > > + xlnx,has-ecc: > + $ref: /schemas/types.yaml#/definitions/flag > + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) > + > required: > - compatible > - reg > @@ -137,6 +141,7 @@ examples: > interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; > tx-fifo-depth = <0x40>; > rx-fifo-depth = <0x40>; > + xlnx,has-ecc; > }; > > - | > -- > 2.1.1 >
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..8d4e5af 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - |
ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. 'xlnx,has-ecc' is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> --- Changes in v5: Update property description Changes in v4: Fix binding check warning Update property description Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+)