| Message ID | 1693557645-2728466-2-git-send-email-srinivas.goud@amd.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | can: xilinx_can: Add ECC feature support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On 01.09.2023 14:10:43, Srinivas Goud wrote: > ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. > Part of this feature configuration and counter registers added in > IP for 1bit/2bit ECC errors. > > xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller > node if ECC block enabled in the HW > > Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> > --- > Changes in v4: > Fix binding check warning > Update property description > > Changes in v3: > Update commit description > > Changes in v2: > None > > Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > index 64d57c3..50a2671 100644 > --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > @@ -49,6 +49,10 @@ properties: > resets: > maxItems: 1 > > + xlnx,has-ecc: > + $ref: /schemas/types.yaml#/definitions/flag > + description: CAN Tx and Rx fifo has ECC (AXI CAN) Are there 2 FIFOs? If so I'd phrase it this way: "CAN TX and RX FIFOs have ECC support (AXI CAN)" - or - "CAN TX and RX FIFOs support ECC" Marc
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..50a2671 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN Tx and Rx fifo has ECC (AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - |
ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> --- Changes in v4: Fix binding check warning Update property description Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+)