| Message ID | 1693234725-3615719-2-git-send-email-srinivas.goud@amd.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | can: xilinx_can: Add ECC feature support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | fail | build log |
On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote: > ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. > Part of this feature configuration and counter registers added in > IP for 1bit/2bit ECC errors. > > xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller > node if ECC block enabled in the HW > > Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> > --- > Changes in v3: > Update commit description > > Changes in v2: > None Doesn't apply, dependency? > > Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > index 64d57c3..c842610 100644 > --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml > @@ -49,6 +49,10 @@ properties: > resets: > maxItems: 1 > > + xlnx,has-ecc: > + $ref: /schemas/types.yaml#/definitions/flag > + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) has ECC or enable ECC? > + > required: > - compatible > - reg > @@ -137,6 +141,7 @@ examples: > interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; > tx-fifo-depth = <0x40>; > rx-fifo-depth = <0x40>; > + xlnx,has-ecc Obviously not tested. > }; > > - | > -- > 2.1.1 >
Hi Rob, >-----Original Message----- >From: Rob Herring <robh@kernel.org> >Sent: Monday, August 28, 2023 9:13 PM >To: Goud, Srinivas <srinivas.goud@amd.com> >Cc: wg@grandegger.com; mkl@pengutronix.de; davem@davemloft.net; >edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; >krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; >p.zabel@pengutronix.de; git (AMD-Xilinx) <git@amd.com>; Simek, Michal ><michal.simek@amd.com>; linux-can@vger.kernel.org; linux-arm- >kernel@lists.infradead.org; linux-kernel@vger.kernel.org; >netdev@vger.kernel.org; devicetree@vger.kernel.org; >appana.durga.rao@xilinx.com; naga.sureshkumar.relli@xilinx.com >Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property >'xlnx,has-ecc' > >On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote: >> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. >> Part of this feature configuration and counter registers added in IP >> for 1bit/2bit ECC errors. >> >> xlnx,has-ecc is optional property and added to Xilinx AXI CAN >> Controller node if ECC block enabled in the HW >> >> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> >> --- >> Changes in v3: >> Update commit description >> >> Changes in v2: >> None > >Doesn't apply, dependency? This patch is created on top of below commit and this is part of the linux-can-next/master and Linux torvalds GIT https://lore.kernel.org/all/bfaed896cc51af02fe5f290675313ab4dcab0d33.1689164442.git.michal.simek@amd.com/ > >> >> Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> index 64d57c3..c842610 100644 >> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> @@ -49,6 +49,10 @@ properties: >> resets: >> maxItems: 1 >> >> + xlnx,has-ecc: >> + $ref: /schemas/types.yaml#/definitions/flag >> + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) > >has ECC or enable ECC? Will update description with "has ECC" > >> + >> required: >> - compatible >> - reg >> @@ -137,6 +141,7 @@ examples: >> interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; >> tx-fifo-depth = <0x40>; >> rx-fifo-depth = <0x40>; >> + xlnx,has-ecc > >Obviously not tested. Will fix it. Thanks, Srinivas
On 30/08/2023 08:06, Goud, Srinivas wrote: >>> + >>> required: >>> - compatible >>> - reg >>> @@ -137,6 +141,7 @@ examples: >>> interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; >>> tx-fifo-depth = <0x40>; >>> rx-fifo-depth = <0x40>; >>> + xlnx,has-ecc >> >> Obviously not tested. > Will fix it. > Fix it by fixing error or by testing? Can you do both? Best regards, Krzysztof
Hi Krzysztof, >-----Original Message----- >From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >Sent: Wednesday, August 30, 2023 12:43 PM >To: Goud, Srinivas <srinivas.goud@amd.com>; Rob Herring <robh@kernel.org> >Cc: wg@grandegger.com; mkl@pengutronix.de; davem@davemloft.net; >edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; >krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; >p.zabel@pengutronix.de; git (AMD-Xilinx) <git@amd.com>; Simek, Michal ><michal.simek@amd.com>; linux-can@vger.kernel.org; linux-arm- >kernel@lists.infradead.org; linux-kernel@vger.kernel.org; >netdev@vger.kernel.org; devicetree@vger.kernel.org; >appana.durga.rao@xilinx.com; naga.sureshkumar.relli@xilinx.com >Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property >'xlnx,has-ecc' > >On 30/08/2023 08:06, Goud, Srinivas wrote: >>>> + >>>> required: >>>> - compatible >>>> - reg >>>> @@ -137,6 +141,7 @@ examples: >>>> interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; >>>> tx-fifo-depth = <0x40>; >>>> rx-fifo-depth = <0x40>; >>>> + xlnx,has-ecc >>> >>> Obviously not tested. >> Will fix it. >> > >Fix it by fixing error or by testing? Can you do both? Tested with v1 and missed in v2 due to copy paste, will test and send next version. Thanks. Srinivas
diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..c842610 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc }; - |
ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> --- Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+)