| Message ID | 1605172274-44916-1-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/2] RISC-V: Update l2 cache DT documentation to add support for SiFive FU740 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success |
On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > compared to 3 in FU540. Update the DT documentation accordingly with > "compatible" and "interrupt" property changes. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++----- > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > index efc0198..4873d5c 100644 > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > @@ -27,6 +27,7 @@ select: > items: > - enum: > - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > > required: > - compatible > @@ -34,7 +35,9 @@ select: > properties: > compatible: > items: > - - const: sifive,fu540-c000-ccache > + - enum: > + - sifive,fu540-c000-ccache > + - sifive,fu740-c000-ccache > - const: cache > > cache-block-size: > @@ -51,12 +54,6 @@ properties: > > cache-unified: true > > - interrupts: > - description: | > - Must contain entries for DirError, DataError and DataFail signals. > - minItems: 3 > - maxItems: 3 Keep this here and just change maxItems to 4. Really, what each interrupt is should be listed out as an 'items' entry. > - > reg: > maxItems: 1 > > @@ -67,6 +64,28 @@ properties: > The reference to the reserved-memory for the L2 Loosely Integrated Memory region. > The reserved memory node should be defined as per the bindings in reserved-memory.txt. > > +if: > + properties: > + compatible: > + contains: > + const: sifive,fu540-c000-ccache > + > +then: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DataError and DataFail signals. > + minItems: 3 > + maxItems: 3 Here you just need 'maxItems: 3'. > + > +else: > + properties: > + interrupts: > + description: | > + Must contain entries for DirError, DirFail, DataError, DataFail signals. DirFail should be last so you keep the same indices. > + minItems: 4 > + maxItems: 4 And 'minItems: 4' > + > additionalProperties: false > > required: > -- > 2.7.4 >
> -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 21 November 2020 18:25 > To: Yash Shah <yash.shah@openfive.com> > Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; > palmer@dabbelt.com; aou@eecs.berkeley.edu; > Jonathan.Cameron@huawei.com; wsa@kernel.org; sam@ravnborg.org; > Sagar Kadam <sagar.kadam@openfive.com>; anup@brainfault.org; > bp@suse.de; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; > linux-kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@openfive.com> > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add > support for SiFive FU740 > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > > compared to 3 in FU540. Update the DT documentation accordingly with > > "compatible" and "interrupt" property changes. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 > > +++++++++++++++++----- > > 1 file changed, 26 insertions(+), 7 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > index efc0198..4873d5c 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml <...> > > @@ -51,12 +54,6 @@ properties: > > > > cache-unified: true > > > > - interrupts: > > - description: | > > - Must contain entries for DirError, DataError and DataFail signals. > > - minItems: 3 > > - maxItems: 3 > > Keep this here and just change maxItems to 4. Really, what each interrupt is > should be listed out as an 'items' entry. > Sure will send a v2 with the above modifications. <...> > > > + > > +else: > > + properties: > > + interrupts: > > + description: | > > + Must contain entries for DirError, DirFail, DataError, DataFail signals. > > DirFail should be last so you keep the same indices. Actually, the interrupts have been numbered like that in FU740 SoCs and the driver expects the interrupts to be in this order. I will keep the same order for v2 as well. Let me know if you still disagree. Thanks for your review. - Yash
On Mon, Nov 23, 2020 at 3:32 AM Yash Shah <yash.shah@openfive.com> wrote: > > > -----Original Message----- > > From: Rob Herring <robh@kernel.org> > > Sent: 21 November 2020 18:25 > > To: Yash Shah <yash.shah@openfive.com> > > Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; > > palmer@dabbelt.com; aou@eecs.berkeley.edu; > > Jonathan.Cameron@huawei.com; wsa@kernel.org; sam@ravnborg.org; > > Sagar Kadam <sagar.kadam@openfive.com>; anup@brainfault.org; > > bp@suse.de; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; > > linux-kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@openfive.com> > > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add > > support for SiFive FU740 > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote: > > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as > > > compared to 3 in FU540. Update the DT documentation accordingly with > > > "compatible" and "interrupt" property changes. > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > --- > > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 > > > +++++++++++++++++----- > > > 1 file changed, 26 insertions(+), 7 deletions(-) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > index efc0198..4873d5c 100644 > > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml > > <...> > > > > @@ -51,12 +54,6 @@ properties: > > > > > > cache-unified: true > > > > > > - interrupts: > > > - description: | > > > - Must contain entries for DirError, DataError and DataFail signals. > > > - minItems: 3 > > > - maxItems: 3 > > > > Keep this here and just change maxItems to 4. Really, what each interrupt is > > should be listed out as an 'items' entry. > > > > Sure will send a v2 with the above modifications. > > <...> > > > > > > + > > > +else: > > > + properties: > > > + interrupts: > > > + description: | > > > + Must contain entries for DirError, DirFail, DataError, DataFail signals. > > > > DirFail should be last so you keep the same indices. > > Actually, the interrupts have been numbered like that in FU740 SoCs and the driver expects the interrupts to be in this order. > I will keep the same order for v2 as well. Let me know if you still disagree. Numbered within the cache block or the interrupt controller? If the former, then fine. The latter would be outside the scope of the binding. Another SoC could hook up interrupts differently. It's going to be easier for the driver to deal with 1 new irq index rather than 2 whole sets of different indices, but if you want to do it the hard way... Rob
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml index efc0198..4873d5c 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml @@ -27,6 +27,7 @@ select: items: - enum: - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache required: - compatible @@ -34,7 +35,9 @@ select: properties: compatible: items: - - const: sifive,fu540-c000-ccache + - enum: + - sifive,fu540-c000-ccache + - sifive,fu740-c000-ccache - const: cache cache-block-size: @@ -51,12 +54,6 @@ properties: cache-unified: true - interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. - minItems: 3 - maxItems: 3 - reg: maxItems: 1 @@ -67,6 +64,28 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. +if: + properties: + compatible: + contains: + const: sifive,fu540-c000-ccache + +then: + properties: + interrupts: + description: | + Must contain entries for DirError, DataError and DataFail signals. + minItems: 3 + maxItems: 3 + +else: + properties: + interrupts: + description: | + Must contain entries for DirError, DirFail, DataError, DataFail signals. + minItems: 4 + maxItems: 4 + additionalProperties: false required:
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the DT documentation accordingly with "compatible" and "interrupt" property changes. Signed-off-by: Yash Shah <yash.shah@sifive.com> --- .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++----- 1 file changed, 26 insertions(+), 7 deletions(-)