From patchwork Wed Nov 4 09:40:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1393755 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=IiyP6tIs; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CR1qZ3KDhz9sTK for ; Wed, 4 Nov 2020 20:40:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729097AbgKDJk4 (ORCPT ); Wed, 4 Nov 2020 04:40:56 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:31012 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729086AbgKDJkz (ORCPT ); Wed, 4 Nov 2020 04:40:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1604482855; x=1636018855; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=FTnpt332R5NLvCQFqroGbAzktlAA+XgpwzFNaC+ewTk=; b=IiyP6tIs8LRwLCmMxlGG5Se36xxX1S5fXDw+CW+AJU/itsztvX9mZujO pPPnCMEGgi71n5k//rm0hB5e6Wm3L6UvE2VDSw2sFvR1CADlWyL5ALzBW sS3SY0O07P5oAO90btjzWC2KWpOPRyZe0NWEzX0Lt0CWagr/K3quVdvKG IR5SePyrC98xRyBEukPEUoLg7K/13gXDBV1GFaDKuuWVbbbPS/MJ9ogBw m6PLQPlYOAM+eLfFWE9YywglksYa4bGjNjde8JrLU9gtmfo3cVkg6W7hX 47I1NrTj6J5TsO3yR9dlWQ6cgU36ieyeQhFO1a3EL2+Ylauhdx7rAJ59N Q==; IronPort-SDR: 4WsZQFbql3yw6035MST7ldq15zB5TODG0I/nSHQPw+SmShSTfETls8hiqR0L2/NlHZVpAA6nH1 bqpU8OmdW1XvmbZqkbPLiHQwQzFPKZEXSuKdX/GpVzXETRd6mbydl59o+OLUkmaJleCVKwXBOQ QrIJRNA0OevkZX9hm15FaW4TTB6zhdaM+AtkeiS8TIzNUkEWqAXbhFYPx/OsFeo1+HZ3Me3EmA B8Yry4tc3my6f90pYImXut9XAtcKmWOZVe+srIZqjchwyKj8eLeu1fpmt/ie+PasgCWqGVWWBp 1hE= X-IronPort-AV: E=Sophos;i="5.77,450,1596524400"; d="scan'208";a="102141446" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Nov 2020 02:40:54 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 4 Nov 2020 02:40:54 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 4 Nov 2020 02:40:49 -0700 From: Claudiu Beznea To: , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 8/8] clk: at91: sama7g5: register cpu clock Date: Wed, 4 Nov 2020 11:40:02 +0200 Message-ID: <1604482802-1647-9-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604482802-1647-1-git-send-email-claudiu.beznea@microchip.com> References: <1604482802-1647-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Register CPU clock as being the master clock prescaler. This would be used by DVFS. The block diagram of SAMA7G5's PMC contains also a divider between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the frequencies supported by SAMA7G5 could be directly received from CPUPLL + master clock prescaler and the extra divider would do no work in case it would be enabled. Signed-off-by: Claudiu Beznea --- drivers/clk/at91/sama7g5.c | 13 ++++++------- include/dt-bindings/clock/at91.h | 1 + 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index d38766c6fc8c..b712dd273a0b 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -852,7 +852,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, + sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); @@ -929,18 +929,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np) } } - parent_names[0] = md_slck_name; - parent_names[1] = "mainck"; - parent_names[2] = "cpupll_divpmcck"; - parent_names[3] = "syspll_divpmcck"; - hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, + parent_names[0] = "cpupll_divpmcck"; + hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_SET_RATE_PARENT, 0); if (IS_ERR(hw)) goto err_free; - hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", + sama7g5_pmc->chws[PMC_CPU] = hw; + + hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, 0); if (IS_ERR(hw)) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index fab313f62e8f..98e1b2ab6403 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -34,6 +34,7 @@ #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) #define PMC_AUDIOIOPLL (PMC_MAIN + 7) #define PMC_ETHPLL (PMC_MAIN + 8) +#define PMC_CPU (PMC_MAIN + 9) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */