| Message ID | 1599457679-8947-2-git-send-email-yash.shah@sifive.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | SiFive DDR controller and EDAC support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success |
On Mon, Sep 07, 2020 at 11:17:57AM +0530, Yash Shah wrote: > Add device tree bindings for SiFive FU540 DDR controller driver > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> > Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> > --- > .../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++++++++++++++++++++++ Bindings are organized by function, not vendor/arch generally. This goes in bindings/memory-controllers/. > 1 file changed, 41 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > new file mode 100644 > index 0000000..0288119 > --- /dev/null > +++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml > @@ -0,0 +1,41 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive DDR memory controller binding > + > +description: | > + The Sifive DDR controller driver is used to manage the Cadence DDR > + controller present in SiFive FU540-C000 SoC. Currently the driver is > + used to manage EDAC feature of the DDR controller. Bindings describe h/w not drivers. What a driver supports is irrelevant. > + > +maintainers: > + - Yash Shah <yash.shah@sifive.com> > + > +properties: > + compatible: > + enum: > + - sifive,fu540-c000-ddr > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - | > + memory-controller@100b0000 { > + compatible = "sifive,fu540-c000-ddr"; > + reg = <0x100b0000 0x4000>; > + interrupts = <31>; > + }; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml new file mode 100644 index 0000000..0288119 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive-ddr.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sifive-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive DDR memory controller binding + +description: | + The Sifive DDR controller driver is used to manage the Cadence DDR + controller present in SiFive FU540-C000 SoC. Currently the driver is + used to manage EDAC feature of the DDR controller. + +maintainers: + - Yash Shah <yash.shah@sifive.com> + +properties: + compatible: + enum: + - sifive,fu540-c000-ddr + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@100b0000 { + compatible = "sifive,fu540-c000-ddr"; + reg = <0x100b0000 0x4000>; + interrupts = <31>; + };