From patchwork Wed Aug 5 02:50:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 1341061 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BLx7f5ySfz9sRK for ; Wed, 5 Aug 2020 12:55:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727054AbgHECzX (ORCPT ); Tue, 4 Aug 2020 22:55:23 -0400 Received: from inva021.nxp.com ([92.121.34.21]:46422 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725999AbgHECzW (ORCPT ); Tue, 4 Aug 2020 22:55:22 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7F9DF2013A5; Wed, 5 Aug 2020 04:55:20 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 43E6B20139E; Wed, 5 Aug 2020 04:55:16 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C0295402E5; Wed, 5 Aug 2020 04:55:10 +0200 (CEST) From: Anson Huang To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, aisheng.dong@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH 2/2] dt-bindings: fsl: Convert i.MX7ULP SIM to json-schema Date: Wed, 5 Aug 2020 10:50:41 +0800 Message-Id: <1596595841-27563-2-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596595841-27563-1-git-send-email-Anson.Huang@nxp.com> References: <1596595841-27563-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the i.MX7ULP SIM binding to DT schema format using json-schema. Signed-off-by: Anson Huang --- .../bindings/arm/freescale/fsl,imx7ulp-sim.txt | 16 ---------- .../bindings/arm/freescale/fsl,imx7ulp-sim.yaml | 36 ++++++++++++++++++++++ 2 files changed, 36 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt deleted file mode 100644 index 7d0c7f0..0000000 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt +++ /dev/null @@ -1,16 +0,0 @@ -Freescale i.MX7ULP System Integration Module ----------------------------------------------- -The system integration module (SIM) provides system control and chip configuration -registers. In this module, chip revision information is located in JTAG ID register, -and a set of registers have been made available in DGO domain for SW use, with the -objective to maintain its value between system resets. - -Required properties: -- compatible: Should be "fsl,imx7ulp-sim". -- reg: Specifies base physical address and size of the register sets. - -Example: -sim: sim@410a3000 { - compatible = "fsl,imx7ulp-sim", "syscon"; - reg = <0x410a3000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml new file mode 100644 index 0000000..8b4aff6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP System Integration Module + +maintainers: + - Anson Huang + +description: | + The system integration module (SIM) provides system control and chip configuration + registers. In this module, chip revision information is located in JTAG ID register, + and a set of registers have been made available in DGO domain for SW use, with the + objective to maintain its value between system resets. + +properties: + compatible: + items: + - const: fsl,imx7ulp-sim + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + sim@410a3000 { + compatible = "fsl,imx7ulp-sim", "syscon"; + reg = <0x410a3000 0x1000>; + };