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[06/14] dt-bindings: power: Add r8a774e1 SYSC power domain definitions

Message ID 1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
State Not Applicable
Headers show
Series Add core support for Renesas RZ/G2H SoC | expand

Checks

Context Check Description
robh/checkpatch success

Commit Message

Lad Prabhakar July 7, 2020, 4:18 p.m. UTC
From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/dt-bindings/power/r8a774e1-sysc.h | 36 +++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 include/dt-bindings/power/r8a774e1-sysc.h

Comments

Geert Uytterhoeven July 8, 2020, 9:29 a.m. UTC | #1
On Tue, Jul 7, 2020 at 6:18 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
>
> This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.9, in a branch shared by driver
and DT (renesas-r8a774e1-dt-binding-defs).

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h
new file mode 100644
index 000000000000..7edb8161db36
--- /dev/null
+++ b/include/dt-bindings/power/r8a774e1-sysc.h
@@ -0,0 +1,36 @@ 
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774E1_PD_CA57_CPU0		 0
+#define R8A774E1_PD_CA57_CPU1		 1
+#define R8A774E1_PD_CA57_CPU2		 2
+#define R8A774E1_PD_CA57_CPU3		 3
+#define R8A774E1_PD_CA53_CPU0		 5
+#define R8A774E1_PD_CA53_CPU1		 6
+#define R8A774E1_PD_CA53_CPU2		 7
+#define R8A774E1_PD_CA53_CPU3		 8
+#define R8A774E1_PD_A3VP		 9
+#define R8A774E1_PD_CA57_SCU		12
+#define R8A774E1_PD_A3VC		14
+#define R8A774E1_PD_3DG_A		17
+#define R8A774E1_PD_3DG_B		18
+#define R8A774E1_PD_3DG_C		19
+#define R8A774E1_PD_3DG_D		20
+#define R8A774E1_PD_CA53_SCU		21
+#define R8A774E1_PD_3DG_E		22
+#define R8A774E1_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774E1_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */