From patchwork Thu May 21 08:36:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wesley Cheng X-Patchwork-Id: 1295018 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.a=rsa-sha256 header.s=smtp header.b=dUszdQwX; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49SNJS5zvMz9sSW for ; Thu, 21 May 2020 18:36:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728738AbgEUIgg (ORCPT ); Thu, 21 May 2020 04:36:36 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:49273 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728542AbgEUIgg (ORCPT ); Thu, 21 May 2020 04:36:36 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1590050195; h=References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=aZo+KSybveCXJFPXyoW8aJ7eC6Kn0YlHOsLwiJxxttA=; b=dUszdQwX7QAFN0I1KNQQLrfbKdhzH2HFzY31aAJQ71rslhnJ5rskfGlqh6+nIo4giMPlnvjz sK28J8wrMqRp8+qWpAUkm4paiUniDysrdnccxJ8VjmQs2wIGCGp/LlQj8n7XO7gYYtj+pROv nxBfEvs4oPbrRkcV2kRBjXFGDOw= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 5ec63d80eb073d56915bfc96 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 21 May 2020 08:36:16 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9EF42C43395; Thu, 21 May 2020 08:36:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from wcheng-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: wcheng) by smtp.codeaurora.org (Postfix) with ESMTPSA id C2EA8C433CA; Thu, 21 May 2020 08:36:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C2EA8C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=wcheng@codeaurora.org From: Wesley Cheng To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, balbi@kernel.org, gregkh@linuxfoundation.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, jackp@codeaurora.org, Wesley Cheng Subject: [PATCH v2 3/3] dt-bindings: usb: dwc3: Add entry for tx-fifo-resize Date: Thu, 21 May 2020 01:36:09 -0700 Message-Id: <1590050169-30747-4-git-send-email-wcheng@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1590050169-30747-1-git-send-email-wcheng@codeaurora.org> References: <1590050169-30747-1-git-send-email-wcheng@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Re-introduce the comment for the tx-fifo-resize setting for the DWC3 controller. This allows for vendors to control if they require the TX FIFO resizing logic on their HW, as the default FIFO size configurations may already be sufficient. Signed-off-by: Wesley Cheng Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/usb/dwc3.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 9946ff9..489f5da 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -105,7 +105,7 @@ Optional properties: 1-16 (DWC_usb31 programming guide section 1.2.3) to enable periodic ESS TX threshold. - - tx-fifo-resize: determines if the FIFO *has* to be reallocated. + - tx-fifo-resize: determines if the FIFO *has* to be reallocated. - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 register, undefined length INCR burst type enable and INCRx type. When just one value, which means INCRX burst mode enabled. When