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[V2,11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block

Message ID 1554407683-31580-12-git-send-email-vidyas@nvidia.com
State Superseded, archived
Headers show
Series Add Tegra194 PCIe support | expand


Context Check Description
robh/checkpatch warning "total: 1 errors, 1 warnings, 28 lines checked"

Commit Message

Vidya Sagar April 4, 2019, 7:54 p.m. UTC
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys Designware core
based PCIe IP and Universal PHY block.
Changes since [v1]:
* This is a new patch in v2 series

 .../devicetree/bindings/phy/phy-tegra194-p2u.txt   | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
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diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
new file mode 100644
index 000000000000..baf037dfdf4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
@@ -0,0 +1,28 @@ 
+NVIDIA Tegra194 P2U binding
+Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
+Speed) each interfacing with 12 and 8 P2U instances respectively.
+A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
+interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
+Required properties:
+- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
+- reg: Should be the physical address space and length of respective each P2U
+       instance.
+- reg-names: Must include the entry "ctl".
+Required properties for PHY port node:
+- #phy-cells: Defined by generic PHY bindings.  Must be 0.
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+p2u_0: p2u@03e10000 {
+	compatible = "nvidia,tegra194-p2u";
+	reg = <0x03e10000 0x10000>;
+	reg-names = "ctl";
+	#phy-cells = <0>;