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Wed, 7 Nov 2018 15:12:32 +0000 Received: from BN6PR1101MB2243.namprd11.prod.outlook.com ([fe80::c873:c197:d9d6:3bf6]) by BN6PR1101MB2243.namprd11.prod.outlook.com ([fe80::c873:c197:d9d6:3bf6%6]) with mapi id 15.20.1294.034; Wed, 7 Nov 2018 15:12:32 +0000 From: To: , , , , CC: , , , , , , Subject: [PATCH 1/3] dt-bindings: gpio: add sama5d2 PIOBU support Thread-Topic: [PATCH 1/3] dt-bindings: gpio: add sama5d2 PIOBU support Thread-Index: AQHUdqxO5isTeHVINkW+UUYjkq2vOg== Date: Wed, 7 Nov 2018 15:12:32 +0000 Message-ID: <1541603580-17448-2-git-send-email-andrei.stefanescu@microchip.com> References: <1541603580-17448-1-git-send-email-andrei.stefanescu@microchip.com> In-Reply-To: <1541603580-17448-1-git-send-email-andrei.stefanescu@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0901CA0097.eurprd09.prod.outlook.com (2603:10a6:800:7e::23) To BN6PR1101MB2243.namprd11.prod.outlook.com (2603:10b6:405:52::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Andrei.Stefanescu@microchip.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:BN6PR1101MB2257; H:BN6PR1101MB2243.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: v6s6VTzguoZ5Kpm7Tqden+vz1gRP70AhRWnDq7vEXocj2JUauHxAtPyGfR9EOmsijmd9STP2Az3oLu/9+bV2E3SrXZGkS61HgQPkx2ny3ucg95WqyimvPIMJsjhRqNnxgDtqVSBDPcNWib47CAOHsjQhBWvSm9de00p4KR8QVwhHslRQDaHOX0dIZU6r0t07UnIWG9qBc6/uWbcuUEVCCB8MImSu3ER0RLZbZnDEpcTjSZxS53dXlzADMVLzcTvudhE934kN7cg+YUjbB69yQPva/e9NDcwZf7jP88jd4SAIqFN6VSmY033KTAcFXWAZ5l+UTKxIzC5XiPNgVPsREuZRN+hqOAacqKuRNhy+l9w= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 14207d0f-6f6c-4303-1100-08d644c370b9 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2018 15:12:32.2544 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1101MB2257 X-OriginatorOrg: microchip.com Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch describes the compatible and the device tree bindings necessary for the sama5d2 PIOBU GPIO controller driver. Signed-off-by: Andrei Stefanescu --- .../bindings/gpio/gpio-sama5d2-piobu.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sama5d2-piobu.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-sama5d2-piobu.txt b/Documentation/devicetree/bindings/gpio/gpio-sama5d2-piobu.txt new file mode 100644 index 0000000..791ac51 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sama5d2-piobu.txt @@ -0,0 +1,23 @@ +GPIO controller for SAMA5D2 PIOBU pins. + +This pins have the property of not losing their voltage +during Backup/Self-refresh mode. + +These bindings should be set to a node in the dtsi file. + +Required properties: +- compatible: "syscon", "microchip,sama5d2-piobu" +- #gpio-cells: There are 2. The pin number is the + first, the second represents additional + parameters such as GPIO_ACTIVE_HIGH/LOW. +- gpio-controller: Marks the port as GPIO controller. + +Example: + + secumod@fc040000 { + compatible = "syscon", "microchip,sama5d2-piobu"; + reg = <0xfc040000 0x100>; + + gpio-controller; + #gpio-cells = <2>; + };