From patchwork Mon Feb 12 17:26:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 872194 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zgCKQ20HCz9sBZ for ; Tue, 13 Feb 2018 04:27:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753165AbeBLR1U (ORCPT ); Mon, 12 Feb 2018 12:27:20 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5036 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752421AbeBLR1T (ORCPT ); Mon, 12 Feb 2018 12:27:19 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 12 Feb 2018 09:27:23 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 12 Feb 2018 09:27:19 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 12 Feb 2018 09:27:19 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Feb 2018 17:27:19 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 12 Feb 2018 17:27:18 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 12 Feb 2018 17:27:18 +0000 Received: from pchandru-pc.nvidia.com (Not Verified[10.24.37.8]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Feb 2018 09:27:18 -0800 From: Preetham Chandru Ramchandra To: , , , , , CC: , , , , , Preetham Ramchandra Subject: [PATCH V7 1/7] dt-bindings: ahci-tegra: add binding documentation Date: Mon, 12 Feb 2018 22:56:40 +0530 Message-ID: <1518456406-21564-2-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> References: <1518456406-21564-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Preetham Ramchandra This adds bindings documentation for the AHCI controller on Tegra210 Signed-off-by: Preetham Chandru R --- v7: * For Aux register set drop the Tegra210 since this register set also works on Tegra124 * rephrase the sentence for cml1 clock * change the commit subject to include ahci-tegra * drop pll_e since CCF handles it automatically as CML1 is a child clock of it. v4: * changed the commit message * changed 'sata-cold' reset to mandatory for t210 and t124 * Removed the regulators for T210 since these regulators will be enabled in phy driver. v3: * Add AUX register. v2: * change cml1, pll_e and phy regulators as optional for T210. --- .../bindings/ata/nvidia,tegra124-ahci.txt | 35 ++++++++++++++-------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt index 66c83c3e8915..0f4520a00716 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt @@ -1,20 +1,19 @@ -Tegra124 SoC SATA AHCI controller +Tegra SoC SATA AHCI controller Required properties : -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise, - must contain '"nvidia,-ahci", "nvidia,tegra124-ahci"', where - is tegra132. -- reg : Should contain 2 entries: +- compatible : Must be one of: + - Tegra124 : "nvidia,tegra124-ahci" + - Tegra210 : "nvidia,tegra210-ahci" +- reg : Should contain 3 entries: - AHCI register set (SATA BAR5) - SATA register set + - AUX register set - interrupts : Defines the interrupt used by SATA - clocks : Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names : Must include the following entries: - sata - sata-oob - - cml1 - - pll_e - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names : Must include the following entries: @@ -24,9 +23,19 @@ Required properties : - phys : Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. - phy-names : Must include the following entries: - - sata-phy : XUSB PADCTL SATA PHY -- hvdd-supply : Defines the SATA HVDD regulator -- vddio-supply : Defines the SATA VDDIO regulator -- avdd-supply : Defines the SATA AVDD regulator -- target-5v-supply : Defines the SATA 5V power regulator -- target-12v-supply : Defines the SATA 12V power regulator + - For T124: + - sata-phy : XUSB PADCTL SATA PHY + - For T210: + - sata-0 +- For T124: + - hvdd-supply : Defines the SATA HVDD regulator + - vddio-supply : Defines the SATA VDDIO regulator + - avdd-supply : Defines the SATA AVDD regulator + - target-5v-supply : Defines the SATA 5V power regulator + - target-12v-supply : Defines the SATA 12V power regulator + +Optional properties: +- clock-names : + - cml1 : + cml1 clock should be defined here if the PHY driver + doesn't manage them. If it does, they should not be.