From patchwork Fri Jan 12 14:22:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 859962 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zJ4pP6TZGz9sNw for ; Sat, 13 Jan 2018 01:27:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934049AbeALOXr (ORCPT ); Fri, 12 Jan 2018 09:23:47 -0500 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:52612 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933687AbeALOXp (ORCPT ); Fri, 12 Jan 2018 09:23:45 -0500 X-IronPort-AV: E=Sophos;i="5.46,349,1511852400"; d="scan'208";a="10394888" Received: from exsmtp03.microchip.com (HELO email.microchip.com) ([198.175.253.49]) by esa2.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 12 Jan 2018 07:23:44 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.76.4) by chn-sv-exch03.mchp-main.com (10.10.76.49) with Microsoft SMTP Server id 14.3.352.0; Fri, 12 Jan 2018 07:23:44 -0700 From: Claudiu Beznea To: , , , , , , , , , CC: , , , , , , , Claudiu Beznea , Alexander Shiyan Subject: [PATCH v2 04/16] pwm: clps711x: update documentation regarding pwm-cells Date: Fri, 12 Jan 2018 16:22:51 +0200 Message-ID: <1515766983-15151-5-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515766983-15151-1-git-send-email-claudiu.beznea@microchip.com> References: <1515766983-15151-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org pwm-cells should be at least 2 to provide channel number and period value. Cc: Alexander Shiyan Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt index c0b2028238d6..57f480a872e3 100644 --- a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt @@ -4,12 +4,12 @@ Required properties: - compatible: Shall contain "cirrus,ep7209-pwm". - reg: Physical base address and length of the controller's registers. - clocks: phandle + clock specifier pair of the PWM reference clock. -- #pwm-cells: Should be 1. The cell specifies the index of the channel. +- #pwm-cells: Should be 2. The cell specifies the index of the channel. Example: pwm: pwm@80000400 { compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm"; reg = <0x80000400 0x4>; clocks = <&clks 8>; - #pwm-cells = <1>; + #pwm-cells = <2>; };