From patchwork Thu Oct 26 11:48:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 830575 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yN4zS4hv3z9sBd for ; Thu, 26 Oct 2017 22:49:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751597AbdJZLtH (ORCPT ); Thu, 26 Oct 2017 07:49:07 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:25146 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751251AbdJZLtG (ORCPT ); Thu, 26 Oct 2017 07:49:06 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9QBhpV2017230; Thu, 26 Oct 2017 13:48:17 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2dtg42s64a-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Oct 2017 13:48:17 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 70ADB34; Thu, 26 Oct 2017 11:48:16 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4636C2653; Thu, 26 Oct 2017 11:48:16 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.352.0; Thu, 26 Oct 2017 13:48:16 +0200 Received: from localhost (10.201.23.32) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Thu, 26 Oct 2017 13:48:15 +0200 From: Philippe Cornu To: Rob Herring , Arnd Bergmann , "Russell King" , Mark Rutland , "Yannick Fertre" , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , David Airlie , , , , CC: Fabien Dessenne , Mickael Reulier , Gabriel Fernandez , Ludovic Barre , Alexandre Torgue , Maxime Coquelin Subject: [PATCH v1 1/2] dt-bindings: display: stm32: add a 2nd endpoint Date: Thu, 26 Oct 2017 13:48:08 +0200 Message-ID: <1509018489-19641-2-git-send-email-philippe.cornu@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509018489-19641-1-git-send-email-philippe.cornu@st.com> References: <1509018489-19641-1-git-send-email-philippe.cornu@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-26_03:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ltdc can have up to 2 endpoints: - dpi external gpios: for rgb panels or external bridge ICs. - dpi internal ios: connected internally to dsi. Note: Refer to the reference manual to know if the dsi is present on your device. Signed-off-by: Philippe Cornu Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 74b5ac7..0292522 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -10,7 +10,11 @@ - "lcd" for the clock feeding the output pixel clock & IP clock. - resets: reset to be used by the device (defined by use of RCC macro). Required nodes: - - Video port for RGB output. + - Video port for DPI RGB output: ltdc has one video port with up to 2 + endpoints: + - for external dpi rgb panel or bridge, using gpios. + - for internal dpi input of the MIPI DSI host controller. + Note: These 2 endpoints cannot be activated simultaneously. * STMicroelectronics STM32 DSI controller specific extensions to Synopsys DesignWare MIPI DSI host controller