From patchwork Thu Oct 12 09:37:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 824741 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCQkq37CKz9t2l for ; Thu, 12 Oct 2017 20:38:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755880AbdJLJhz (ORCPT ); Thu, 12 Oct 2017 05:37:55 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:41814 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755797AbdJLJhv (ORCPT ); Thu, 12 Oct 2017 05:37:51 -0400 Received: from ayla.of.borg ([84.195.106.246]) by baptiste.telenet-ops.be with bizsmtp id LZdq1w00J5JzmfG01ZdqWq; Thu, 12 Oct 2017 11:37:50 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1e2Zw6-0005Oy-BW; Thu, 12 Oct 2017 11:37:50 +0200 Received: from geert by ramsan with local (Exim 4.86_2) (envelope-from ) id 1e2Zw6-00038c-AR; Thu, 12 Oct 2017 11:37:50 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Chris Brandt , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH] clk: renesas: rz: clk-rz is meant for RZ/A1 Date: Thu, 12 Oct 2017 11:37:48 +0200 Message-Id: <1507801068-12024-1-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZ family of Renesas SoCs has several different subfamilies (RZ/A, RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT bindings and clk-rz driver apply to RZ/A1 only. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman Acked-by: Rob Herring --- To be queued in clk-renesas-for-v4.15. Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | 4 ++-- drivers/clk/renesas/clk-rz.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt index bb5d942075fbf0bf..8ff3e2774ed8d1d0 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt @@ -1,6 +1,6 @@ -* Renesas RZ Clock Pulse Generator (CPG) +* Renesas RZ/A1 Clock Pulse Generator (CPG) -The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable +The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable CPU and GPU clocks, and several fixed ratio dividers. The CPG also provides a Clock Domain for SoC devices, in combination with the CPG Module Stop (MSTP) Clocks. diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index 5adb934326d1f5be..127c58135c8fec76 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c @@ -1,5 +1,5 @@ /* - * rz Core CPG Clocks + * RZ/A1 Core CPG Clocks * * Copyright (C) 2013 Ideas On Board SPRL * Copyright (C) 2014 Wolfram Sang, Sang Engineering