From patchwork Mon Jul 17 13:19:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 789477 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xB3p30c3bz9sRg for ; Mon, 17 Jul 2017 23:20:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751306AbdGQNU5 (ORCPT ); Mon, 17 Jul 2017 09:20:57 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:35425 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751281AbdGQNU4 (ORCPT ); Mon, 17 Jul 2017 09:20:56 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6HDIt4s005230; Mon, 17 Jul 2017 15:20:06 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2brshhhc7k-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 17 Jul 2017 15:20:06 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C9B9B31; Mon, 17 Jul 2017 13:20:05 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A45632748; Mon, 17 Jul 2017 13:20:05 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.339.0; Mon, 17 Jul 2017 15:20:05 +0200 Received: from localhost (10.201.23.32) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Mon, 17 Jul 2017 15:20:05 +0200 From: Philippe CORNU To: Alexandre Torgue , Thierry Reding , David Airlie , Maxime Coquelin , Russell King , "Mark Rutland" , Rob Herring , "Arnd Bergmann" , Benjamin Gaignard , Yannick Fertre , Archit Taneja , Andrzej Hajda CC: Philippe Cornu , Mickael Reulier , Gabriel Fernandez , Vincent Abriou , Fabien Dessenne , Ludovic Barre , , , Subject: [PATCH v3 2/3] dt-bindings: display: panel: Add support for Orise Tech otm8009a dsi panel Date: Mon, 17 Jul 2017 15:19:52 +0200 Message-ID: <1500297593-30633-3-git-send-email-philippe.cornu@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500297593-30633-1-git-send-email-philippe.cornu@st.com> References: <1500297593-30633-1-git-send-email-philippe.cornu@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-17_10:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using a MIPI-DSI video interface. Its backlight is managed through the DSI link. Signed-off-by: Philippe CORNU Acked-by: Rob Herring --- .../bindings/display/panel/orisetech,otm8009a.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt new file mode 100644 index 0000000..6862028 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt @@ -0,0 +1,21 @@ +Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode) + +The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using +a MIPI-DSI video interface. Its backlight is managed through the DSI link. + +Required properties: + - compatible: "orisetech,otm8009a" + - reg: the virtual channel number of a DSI peripheral + +Optional properties: + - reset-gpios: a GPIO spec for the reset pin (active low). + +Example: +&dsi { + ... + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; + }; +};