From patchwork Mon Jun 19 16:28:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 777863 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wrxPD3ZZXz9s7m for ; Tue, 20 Jun 2017 02:33:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751012AbdFSQdf (ORCPT ); Mon, 19 Jun 2017 12:33:35 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:6714 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750965AbdFSQdf (ORCPT ); Mon, 19 Jun 2017 12:33:35 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5JGOMoh019091; Mon, 19 Jun 2017 18:28:17 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2b4svvks59-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 19 Jun 2017 18:28:17 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C167531; Mon, 19 Jun 2017 16:28:16 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 87BF62860; Mon, 19 Jun 2017 16:28:16 +0000 (GMT) Received: from localhost (10.201.23.32) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Mon, 19 Jun 2017 18:28:16 +0200 From: Philippe CORNU To: Alexandre Torgue , Thierry Reding , David Airlie , Maxime Coquelin , Russell King , Mark Rutland , Rob Herring , Arnd Bergmann , Benjamin Gaignard , Yannick Fertre , Neil Armstrong , Archit Taneja , Eric Anholt , Chris Zhong , Andrzej Hajda , Xinliang Liu , , Xinwei Kong , Chen Feng , Mark Yao CC: Philippe Cornu , Mickael Reulier , Gabriel Fernandez , Vincent Abriou , Fabien Dessenne , Ludovic Barre , , , Subject: [PATCH v4 5/6] dt-bindings: display: stm32: Add DSI host driver Date: Mon, 19 Jun 2017 18:28:04 +0200 Message-ID: <1497889685-27349-6-git-send-email-philippe.cornu@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497889685-27349-1-git-send-email-philippe.cornu@st.com> References: <1497889685-27349-1-git-send-email-philippe.cornu@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-19_09:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds documentation of device tree bindings for the STM32 DSI host driver based on the Synopsys DW MIPI DSI bridge driver. Signed-off-by: Philippe CORNU Reviewed-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/display/st,stm32-ltdc.txt | 104 ++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 90a8459..6353d79 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -12,8 +12,40 @@ Required nodes: - Video port for RGB output. -Example: +* STMicroelectronics STM32 DSI specific extensions to Synopsys DesignWare MIPI + DSI host controller +The STMicroelectronics STM32 DSI driver uses the Synopsys DesignWare MIPI +DSI host controller driver. For all mandatory properties & nodes, please refer +to the related documentation in [5]. + +Mandatory properties specific to STM32 DSI: +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. +- compatible: "st,stm32-dsi". +- clock-names: + - phy pll reference clock string name, must be "ref". +- resets: see [5]. +- reset-names: see [5]. + +Mandatory nodes specific to STM32 DSI: +- ports: A node containing DSI input & output port nodes with endpoint + definitions as documented in [3] & [4]. + - port@0: DSI input port node, connected to the ltdc rgb output port. + - port@1: DSI output port node, connected to a panel or a bridge input port. +- panel or bridge node: A node containing the panel or bridge description as + documented in [6]. + - port: panel or bridge port node, connected to the DSI output port (port@1). + +Note: You can find more documentation in the following references +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/reset/reset.txt +[3] Documentation/devicetree/bindings/media/video-interfaces.txt +[4] Documentation/devicetree/bindings/graph.txt +[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt +[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt + +Example 1: RGB panel / { ... soc { @@ -33,3 +65,73 @@ Example: }; }; }; + +Example 2: DSI panel + +/ { + ... + soc { + ... + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F4_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + + port { + ltdc_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + + dsi: dsi@40016c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; + clock-names = "ref", "pclk"; + resets = <&rcc STM32F4_APB2_RESET(DSI)>; + reset-names = "apb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_in_panel>; + }; + }; + + }; + + panel-dsi@0 { + reg = <0>; /* dsi virtual channel (0..3) */ + compatible = ...; + enable-gpios = ...; + + port { + dsi_in_panel: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + }; + + }; + + }; +};