From patchwork Mon May 29 09:38:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 768114 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wbsB72r1Mz9s74 for ; Mon, 29 May 2017 19:38:39 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="dVqUM4DM"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750854AbdE2Jih (ORCPT ); Mon, 29 May 2017 05:38:37 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:36038 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750898AbdE2Jif (ORCPT ); Mon, 29 May 2017 05:38:35 -0400 Received: by mail-wm0-f50.google.com with SMTP id 7so48529446wmo.1 for ; Mon, 29 May 2017 02:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LWeBEfEnGKvUVu/ewZyG+wG3aYrhnXJxPc0p6ukn/ls=; b=dVqUM4DMFr+vsA5XDxHU+0xqX/TAcfSLYrdPf0bbCs8sEFa7tky1tK+mJWlny25QM/ i1ECnppDNu/N+YJeMLvapnUUd0VC3Mjb5emmWihi7QkZwZpwdRb2WUw7cX8FugHg9rJp lshknQFYhxs4KOmuXpnJHysroH3ohzntFmL64= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LWeBEfEnGKvUVu/ewZyG+wG3aYrhnXJxPc0p6ukn/ls=; b=DE0FTpr7IabRnBbS9VHC0Fv00exoEOOqsG8Z4VVF776XjTu0m0ebZxkMKec7N/EnQO 4thxjrK4Jf5XZuD4gKalz6lggykJAzixCNK+im0Zdopvlp71R/l0cXbjWpaM6419yR/z JEVoi38hCOg2LYBuz7U/m+VUe/jZz1+v7XCXFukblNPjNVGd/emqV49TdF0HkvxJH266 mNsLisFVRvclBdWlmBcQMLdHxCK47xoRilblNF2ebbfCqj6XCVN1igFbp19087s0mVd7 niMR+8TnTXlmJJkFvjbU4BXxIvKUbGyx7XzpWukJhV6cFbKhadPTJ2myOCRQ8XOJPq0S Ol3w== X-Gm-Message-State: AODbwcB6J3wRuFjAQK/PinbescqquS58GtzTISpeEybZQs9sUf+vh2ip TaJH7rORLQkmQ5pF X-Received: by 10.28.131.15 with SMTP id f15mr9066510wmd.47.1496050714168; Mon, 29 May 2017 02:38:34 -0700 (PDT) Received: from lmenx321.st.com. ([80.215.96.223]) by smtp.gmail.com with ESMTPSA id 201sm14015238wmh.22.2017.05.29.02.38.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 29 May 2017 02:38:33 -0700 (PDT) From: Benjamin Gaignard To: yannick.fertre@st.com, alexandre.torgue@st.com, hverkuil@xs4all.nl, devicetree@vger.kernel.org, linux-media@vger.kernel.org, robh@kernel.org, hans.verkuil@cisco.com Cc: Benjamin Gaignard Subject: [PATCH v5 1/2] dt-bindings: media: stm32 cec driver Date: Mon, 29 May 2017 11:38:04 +0200 Message-Id: <1496050685-14301-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496050685-14301-1-git-send-email-benjamin.gaignard@linaro.org> References: <1496050685-14301-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings documentation for stm32 CEC driver. Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/media/st,stm32-cec.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-cec.txt diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt new file mode 100644 index 0000000..6be2381 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.txt @@ -0,0 +1,19 @@ +STMicroelectronics STM32 CEC driver + +Required properties: + - compatible : value should be "st,stm32-cec" + - reg : Physical base address of the IP registers and length of memory + mapped region. + - clocks : from common clock binding: handle to CEC clocks + - clock-names : from common clock binding: must be "cec" and "hdmi-cec". + - interrupts : CEC interrupt number to the CPU. + +Example for stm32f746: + +cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; +};