From patchwork Tue May 23 14:16:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 766010 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wXHfH6pfSz9sP4 for ; Wed, 24 May 2017 00:17:11 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TIMFYyDZ"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030396AbdEWORI (ORCPT ); Tue, 23 May 2017 10:17:08 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:34385 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030395AbdEWORB (ORCPT ); Tue, 23 May 2017 10:17:01 -0400 Received: by mail-pf0-f175.google.com with SMTP id 9so116051709pfj.1 for ; Tue, 23 May 2017 07:17:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TCzWnzJHkW2SFRPz4eiJs5qhJ0x1GgU4cRW9E8ItAJo=; b=TIMFYyDZm1+SkblPq9cRtqz3IHGWRzOszDOI62fkRZJ7Yz2jKK0iB3/adGr5UgnqKr SIO6LvcpOlWLEx3Q7ntMZU71tFEhpQGEzLxRRipUxw4QXUivsBRF0sh2Cmpotjre/3JX MEtHvp9Wkx6m/4zoNIfS8SN6MNZLFRScV0qiI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TCzWnzJHkW2SFRPz4eiJs5qhJ0x1GgU4cRW9E8ItAJo=; b=jC8UeOuPG7TBRPItK1vMQAiMBf4ljFqnm6xMYyZ9Ebg+loCfFtuZb4kdtHXdRm3URa 1bYcpIAE+XvEXnNR6xrgFkL5OhE+aE0xM2RizVyniIQ8NPko6Wfjdc3+M5ZgkRv4CtOl SAgW9LajW3A4MK9WEwPc/GydZuPveLsjo9f7IxlsK4+/KThRbC3kGVfqG0hZVvYpBN/p JQ6E+Ig2qbIyteOTS0fNYSEWCYDNEsdYW9DwaIyJZQVbWvQRR/hKilqO+bbxbKpek5HX b0NfM678JtYENZajCEoCLzbTmPRNGX/yoTYn5tvc8BoBxNDRT54IuxVlVAEITincnaBy HRZA== X-Gm-Message-State: AODbwcAPJiWAOMK1EBDkcNdsTg24020ocbxIQHSS3Ogyoa2CkU+zS7W9 z+TVLC5c2SU988gw X-Received: by 10.98.59.2 with SMTP id i2mr31904774pfa.50.1495549019985; Tue, 23 May 2017 07:16:59 -0700 (PDT) Received: from localhost.localdomain (li1068-205.members.linode.com. [106.184.3.205]) by smtp.gmail.com with ESMTPSA id x80sm1953334pff.105.2017.05.23.07.16.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 May 2017 07:16:58 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Mathieu Poirier , Rob Herring , Mark Rutland , Liviu Dudau , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Greg Kroah-Hartman , Suzuki K Poulose , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Stephen Boyd , Mike Leach Cc: Leo Yan Subject: [PATCH v11 1/9] coresight: bindings for CPU debug module Date: Tue, 23 May 2017 22:16:12 +0800 Message-Id: <1495548980-30432-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495548980-30432-1-git-send-email-leo.yan@linaro.org> References: <1495548980-30432-1-git-send-email-leo.yan@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..2982912 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,49 @@ +* CoreSight CPU Debug Component: + +CoreSight CPU debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be "arm,coresight-cpu-debug"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the CPU phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to the debug power domain. We use "power-domains" + binding to turn on the debug logic if it has own dedicated + power domain and if necessary to use "cpuidle.off=1" or + "nohlt" in the kernel command line or sysfs node to + constrain idle states to ensure registers in the CPU power + domain are accessible. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + };