From patchwork Fri May 12 14:56:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe CORNU X-Patchwork-Id: 761688 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wPY6V2mf1z9s75 for ; Sat, 13 May 2017 00:59:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757044AbdELO7o (ORCPT ); Fri, 12 May 2017 10:59:44 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:39857 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757030AbdELO7o (ORCPT ); Fri, 12 May 2017 10:59:44 -0400 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v4CEscvM001938; Fri, 12 May 2017 16:56:54 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2ad6vrtq79-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 12 May 2017 16:56:54 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 54DDB3F; Fri, 12 May 2017 14:56:52 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 26F502450; Fri, 12 May 2017 14:56:52 +0000 (GMT) Received: from localhost (10.201.23.32) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Fri, 12 May 2017 16:56:52 +0200 From: Philippe CORNU To: Alexandre Torgue , Thierry Reding , David Airlie , Maxime Coquelin , Russell King , Mark Rutland , Rob Herring , Arnd Bergmann , Benjamin Gaignard , Yannick Fertre CC: Philippe Cornu , Mickael Reulier , Gabriel Fernandez , Vincent Abriou , Fabien Dessenne , Ludovic Barre , , , , Subject: [PATCH v1 2/3] dt-bindings: display: Add STM32 DSI host driver Date: Fri, 12 May 2017 16:56:28 +0200 Message-ID: <1494600989-13507-3-git-send-email-philippe.cornu@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494600989-13507-1-git-send-email-philippe.cornu@st.com> References: <1494600989-13507-1-git-send-email-philippe.cornu@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.32] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-12_08:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds documentation of device tree bindings for the STM32 DSI host driver based on the Synopsys DW MIPI DSI driver from Rockchip. Signed-off-by: Philippe CORNU --- .../devicetree/bindings/display/st,stm32-ltdc.txt | 92 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt index 8e14769..a61381b 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt @@ -1,7 +1,6 @@ * STMicroelectronics STM32 lcd-tft display controller - ltdc: lcd-tft display controller host - must be a sub-node of st-display-subsystem Required properties: - compatible: "st,stm32-ltdc" - reg: Physical base address of the IP registers and length of memory mapped region. @@ -13,8 +12,25 @@ Required nodes: - Video port for RGB output. -Example: +* STMicroelectronics STM32 specific extensions to Synopsys Designware MIPI DSI +(similar to "rockchip/dw_mipi_dsi_rockchip.txt") +Required properties: +- #address-cells: Should be <1>. +- #size-cells: Should be <0>. +- compatible: "st,stm32-dsi_host". +- reg: Represent the physical address range of the controller. +- clocks, clock-names: Phandles to the controller's pll reference + clock(ref) and APB clock(pclk). As described in [1]. +- ports: contain a port node with endpoint definitions as defined in [2]. +- resets: list of phandle + reset specifier pairs, as described in [3]. +- reset-names: string reset name, must be "apb". + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/media/video-interfaces.txt +[3] Documentation/devicetree/bindings/reset/reset.txt + +Example 1: RGB panel / { ... soc { @@ -34,3 +50,75 @@ Example: }; }; }; + +Example 2: DSI panel + +/ { + ... + soc { + ... + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F4_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + + port { + ltdc_out_dsi_host: endpoint { + remote-endpoint = <&dsi_host_in>; + }; + }; + }; + + + dsi_host: dsi_host@40016C00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-dsi_host"; + reg = <0x40016C00 0x800>; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; + clock-names = "ref", "pclk"; + resets = <&rcc STM32F4_APB2_RESET(DSI)>; + reset-names = "apb"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_host_in: endpoint { + remote-endpoint = <<dc_out_dsi_host>; + }; + }; + + port@1 { + reg = <1>; + dsi_host_out_panel: endpoint { + remote-endpoint = <&dsi_host_in_panel>; + }; + }; + + }; + + panel-dsi@0 { + reg = <0>; /* dsi virtual channel (0..3) */ + compatible = ...; + enable-gpios = ...; + status = "okay"; + + port { + dsi_host_in_panel: endpoint { + remote-endpoint = <&dsi_host_out_panel>; + }; + }; + + }; + + }; + + }; +};