From patchwork Wed Mar 29 13:25:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 744790 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vtT9R4V56z9ryb for ; Thu, 30 Mar 2017 00:28:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932921AbdC2N1r (ORCPT ); Wed, 29 Mar 2017 09:27:47 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:57226 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754666AbdC2N0Y (ORCPT ); Wed, 29 Mar 2017 09:26:24 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v2TDPdd8015129; Wed, 29 Mar 2017 15:25:46 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 29dgafg6x9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 29 Mar 2017 15:25:46 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CBB6A38; Wed, 29 Mar 2017 13:25:45 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A3CD929D0; Wed, 29 Mar 2017 13:25:45 +0000 (GMT) Received: from localhost (10.201.23.73) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 29 Mar 2017 15:25:45 +0200 From: Hugues Fruchet To: Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Mauro Carvalho Chehab , Hans Verkuil CC: , , , , Benjamin Gaignard , Yannick Fertre , Hugues Fruchet Subject: [PATCH v1 1/8] dt-bindings: Document STM32 DCMI bindings Date: Wed, 29 Mar 2017 15:25:19 +0200 Message-ID: <1490793926-6477-2-git-send-email-hugues.fruchet@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490793926-6477-1-git-send-email-hugues.fruchet@st.com> References: <1490793926-6477-1-git-send-email-hugues.fruchet@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.73] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-29_09:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds documentation of device tree bindings for the STM32 DCMI (Digital Camera Memory Interface). Signed-off-by: Hugues Fruchet --- .../devicetree/bindings/media/st,stm32-dcmi.txt | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dcmi.txt diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt b/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt new file mode 100644 index 0000000..f0dc709 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.txt @@ -0,0 +1,77 @@ +STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) + +Required properties: +- compatible: "st,stm32-dcmi" +- reg: physical base address and length of the registers set for the device; +- interrupts: should contain IRQ line for the DCMI; +- clocks: list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names: must contain "mclk", which is the DCMI peripherial clock. +- resets: Reference to a reset controller +- reset-names: see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt + +DCMI supports a single port node with parallel bus. It should contain one +'port' child node with child 'endpoint' node. Please refer to the bindings +defined in Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + +Device node example +------------------- + dcmi: dcmi@50050000 { + compatible = "st,stm32-dcmi"; + reg = <0x50050000 0x400>; + interrupts = <78>; + resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; + clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&dcmi_pins>; + dmas = <&dma2 1 1 0x414 0x3>; + dma-names = "tx"; + status = "disabled"; + }; + +Board setup example +------------------- + +&dcmi { + status = "okay"; + + port { + dcmi_0: endpoint@0 { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + +{ + [...] + i2c@0 { + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_ext_camera>; + clock-names = "xvclk"; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&dcmi_0>; + }; + }; + }; + }; + + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; +}