From patchwork Tue Mar 21 15:25:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 741632 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vnc971pMqz9s3w for ; Wed, 22 Mar 2017 02:26:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="1IVU0uUv"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758049AbdCUP0N (ORCPT ); Tue, 21 Mar 2017 11:26:13 -0400 Received: from mail-wm0-f46.google.com ([74.125.82.46]:36691 "EHLO mail-wm0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758047AbdCUP0M (ORCPT ); Tue, 21 Mar 2017 11:26:12 -0400 Received: by mail-wm0-f46.google.com with SMTP id n11so14762210wma.1 for ; Tue, 21 Mar 2017 08:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kHBK9Y1bzIeHPJP+ItEo2GRiNL+yUhbE1aqzDTsuylA=; b=1IVU0uUvxcKszIds9KmfyeNkSQUPRZXDW8fjHY1nO/bJ7m746Jo5YQIlcrNub05wI1 25cg1td7PqRjgceNLtVebT4GLC5mL0LbpKx7UGfyHt+fQTJjzWy6RsSOFJpA195iWkEJ XtIG5pCDulpeEpA3/ceb1S9yBaKcLAOh0UdyyMYFAavlTm3Kichztrm7o2oN650janry Fb/6aOMFXAZSSfqVcCpQKwCbWklCwQAd6DtFyiaHPOFdS6pC65o1LCwWRGaEWS+htSxs osavQVmG7EuwOg1jblt1rR7Rz/7xb6x7g+zdGdbQ6VbOHH5zJK+3l0095kffqNHuu88V 90Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kHBK9Y1bzIeHPJP+ItEo2GRiNL+yUhbE1aqzDTsuylA=; b=lfozJDUsbtSOXblWUJjk5m4ifBxJ6WJcVW89iGsAt2DcvriQL9kzc3PC7X1SJyux0L rznPCj7E90nEcsgS1xIvJuhij8U83lGpR8XN8mFEeuFfnpPKVL+C0YEHQ6x5zOPt9YUp +SCDPNzRLuI9KUgIIno4oiXk+JRjUz/SJU+mcUVrapN3CEV1jdQC2YPYcLgd0sz5XZXc vz3rG9bev3mdU6AWHcktseLHlHm+rrWoWmZF9DtrynL2w3yCkePWPQicGiGHS2p5CCFM GTTGx/XPpY89nw8Fo6+UkBGK+81urXNyxv5+49AldxJQ2dBTwDX0CzLUZ+D/77iybPJV WYFw== X-Gm-Message-State: AFeK/H1K5AQ4Gi/QiSMRiSFEOLpCqYoU7w7NTBvOWiw9O9pbmqnJCSNZUt6bLaI72hFrR/5t X-Received: by 10.28.141.201 with SMTP id p192mr3544476wmd.66.1490109965137; Tue, 21 Mar 2017 08:26:05 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id b13sm18088890wmf.6.2017.03.21.08.26.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Mar 2017 08:26:04 -0700 (PDT) From: Neil Armstrong To: airlied@linux.ie Cc: Neil Armstrong , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 10/13] dt-bindings: Add bindings for the Amlogic Meson dw-hdmi extension Date: Tue, 21 Mar 2017 16:25:47 +0100 Message-Id: <1490109950-21421-11-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490109950-21421-1-git-send-email-narmstrong@baylibre.com> References: <1490109950-21421-1-git-send-email-narmstrong@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This binding describes the Amlogic Meson specific extension to the Synopsys Designware HDMI Controller. Acked-by: Rob Herring Signed-off-by: Neil Armstrong --- .../bindings/display/amlogic,meson-dw-hdmi.txt | 111 +++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt new file mode 100644 index 0000000..7f040ed --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt @@ -0,0 +1,111 @@ +Amlogic specific extensions to the Synopsys Designware HDMI Controller +====================================================================== + +The Amlogic Meson Synopsys Designware Integration is composed of : +- A Synopsys DesignWare HDMI Controller IP +- A TOP control block controlling the Clocks and PHY +- A custom HDMI PHY in order to convert video to TMDS signal + ___________________________________ +| HDMI TOP |<= HPD +|___________________________________| +| | | +| Synopsys HDMI | HDMI PHY |=> TMDS +| Controller |________________| +|___________________________________|<=> DDC + +The HDMI TOP block only supports HPD sensing. +The Synopsys HDMI Controller interrupt is routed through the +TOP Block interrupt. +Communication to the TOP Block and the Synopsys HDMI Controller is done +via a pair of dedicated addr+read/write registers. +The HDMI PHY is configured by registers in the HHI register block. + +Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux +selects either the ENCI encoder for the 576i or 480i formats or the ENCP +encoder for all the other formats including interlaced HD formats. + +The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate +DVI timings for the HDMI controller. + +Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare +HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF +audio source interfaces. + +Required properties: +- compatible: value should be different for each SoC family as : + - GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi" + - GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi" + - GXM (S912) : "amlogic,meson-gxm-dw-hdmi" + followed by the common "amlogic,meson-gx-dw-hdmi" +- reg: Physical base address and length of the controller's registers. +- interrupts: The HDMI interrupt number +- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, + and the Amlogic Meson venci clocks as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt, + the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci" +- resets, resets-names: must have the phandles to the HDMI apb, glue and phy + resets as described in : + Documentation/devicetree/bindings/reset/reset.txt, + the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy" + +Required nodes: + +The connections to the HDMI ports are modeled using the OF graph +bindings specified in Documentation/devicetree/bindings/graph.txt. + +The following table lists for each supported model the port number +corresponding to each HDMI output and input. + + Port 0 Port 1 +----------------------------------------- + S905 (GXBB) VENC Input TMDS Output + S905X (GXL) VENC Input TMDS Output + S905D (GXL) VENC Input TMDS Output + S912 (GXM) VENC Input TMDS Output + +Example: + +hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; +}; + +hdmi_tx: hdmi-tx@c883a000 { + compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; + reg = <0x0 0xc883a000 0x0 0x1c>; + interrupts = ; + resets = <&reset RESET_HDMITX_CAPB3>, + <&reset RESET_HDMI_SYSTEM_RESET>, + <&reset RESET_HDMI_TX>; + reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; + clocks = <&clkc CLKID_HDMI_PCLK>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_GCLK_VENCI_INT0>; + clock-names = "isfr", "iahb", "venci"; + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + hdmi_tx_venc_port: port@0 { + reg = <0>; + + hdmi_tx_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + + /* TMDS Output */ + hdmi_tx_tmds_port: port@1 { + reg = <1>; + + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; +};