| Message ID | 1450119456-964-5-git-send-email-geert+renesas@glider.be |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, Dec 14, 2015 at 07:57:13PM +0100, Geert Uytterhoeven wrote: > Amend the DT bindings to include the optional clock sources for the Baud > Rate Generator for External Clock (BRG), as found on some SCIF variants > and on HSCIF. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Cc: devicetree@vger.kernel.org > --- > v3: > - Add Acked-by, > - Rename "int_clk" to "brg_int". > --- > Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++ > 1 file changed, 6 insertions(+) Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 31cc0631ef7ca22d..f4ad30ef1628f8da 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -56,6 +56,12 @@ Required properties: On (H)SCI(F) and some SCIFA, an additional clock may be specified: - "hsck" for the optional external clock input (on HSCIF), - "sck" for the optional external clock input (on other variants). + On UARTs equipped with a Baud Rate Generator for External Clock (BRG) + (some SCIF and HSCIF), additional clocks may be specified: + - "brg_int" for the optional internal clock source for the frequency + divider (typically the (AXI or SHwy) bus clock), + - "scif_clk" for the optional external clock source for the frequency + divider (SCIF_CLK). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node.